Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

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1 - Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring

2 -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties of oolean lgebra.6 The Sum-of-Products Form, and Logic Diagrams.7 The Product-of-Sums Form.8 Positive vs. Negative Logic.9 The Data Sheet. Digital Components. Sequential Logic.2 Design of Finite State Machines.3 Mealy vs. Moore Machines.4 Registers.5 Counters 999 M. Murdocca and V. Heuring

3 -3 Some Definitions Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder. Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit. Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller. 999 M. Murdocca and V. Heuring

4 -4 The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, and, and, or 5 V and V for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. set of inputs i i n are presented to the CLU, which produces a set of outputs according to mapping functions f f m. i i i n... Combinational logic unit... f (i, i ) f (i, i 3, i 4 ) f m (i 9, i n ) 999 M. Murdocca and V. Heuring

5 -5 Truth Table Developed in 854 by George oole. Further developed by Claude Shannon (ell Labs). Outputs are computed for all possible input combinations (how many input combinations are there?) Consider a room with two light switches. How must they work? GND Inputs Output Hot Light Z Z Switch Switch 999 M. Murdocca and V. Heuring

6 -6 lternate ssignment of Outputs to Switch Settings We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior. Inputs Output Z 999 M. Murdocca and V. Heuring

7 -7 Truth Tables Showing ll Possible Functions of Two inary Variables Inputs Outputs The more frequently used functions have names: ND, XOR, OR, NOR, XOR, and NND. (lways use upper case spelling.) False ND XOR OR Inputs Outputs NOR XNOR + + NND True 999 M. Murdocca and V. Heuring

8 -8 Logic Gates and Their Symbols Logic symbols shown for ND, OR, buffer, and NOT oolean functions. F F Note the use of the inversion bubble. F = F = + (e careful about the nose of the gate when drawing ND vs. OR.) ND F OR F F = F = uffer NOT (Inverter) 999 M. Murdocca and V. Heuring

9 M. Murdocca and V. Heuring Logic Gates and their Symbols (cont ) F NND F NOR F = F = + F Exclusive-OR (XOR) F = F Exclusive-NOR (XNOR) F =.

10 - Variations of Logic Gate Symbols C F = C F = + (a) (b) + + (c) (a) 3 inputs (b) Negated input (c) Complementary outputs 999 M. Murdocca and V. Heuring

11 -5 Properties of oolean lgebra Principle of duality: The dual of a oolean function is obtained by replacing ND with OR and OR with ND, s with s, and s with s. Theorems Postulates Relationship Dual Property = ( + C) = + C = = = = + = + + C = ( + ) ( + C) + = + = + = + = Commutative Distributive Identity Complement Zero and one theorems Idempotence ( C) = ( ) C + ( + C) = ( + ) + C ssociative = Involution = + + = DeMorgan s Theorem + C + C = + C ( + ) = ( + )( +C)( +C) = (+)( +C) + = Consensus Theorem bsorption Theorem 999 M. Murdocca and V. Heuring

12 -6 DeMorgan s Theorem = = + + DeMorgan s theorem: + = + = F = + F = 999 M. Murdocca and V. Heuring

13 -7 ll-nnd Implementation of OR NND alone implements all other oolean logic gates M. Murdocca and V. Heuring

14 -8 Sum-of-Products Form: The Majority Function The SOP form for the 3-input majority function is: M = C + C + C + C = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7). Each of the 2 n terms are called minterms, ranging from to 2 n -. Note relationship between minterm number and boolean value. Minterm Index C F -side -side balance tips to the left or right depending on whether there are more s or s. 999 M. Murdocca and V. Heuring

15 -9 ND-OR Implementation of Majority C Gate count is 8, gate input count is 9. C C F C C 999 M. Murdocca and V. Heuring

16 -4 ppendix Digital Logic Fig.4 K-Map of the Majority Function Place a in each cell that has a that minterm. Cells on the outer edge of the map wrap around Minterm Index C F -side C -side balance tips to the left or right depending on whether there are more s or s. The map contains all the minterms. djacent s in the K-map satisfy the complement property of oolean algebra. Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

17 -42 ppendix Digital Logic Fig.42 djacency Groupings for the Majority Function C M= C + C + Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

18 -43 ppendix Digital Logic.43 Minimized ND-OR Circuit for the Majority Function C F M= C + C + Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

19 -44 ppendix Digital Logic Fig.44 Minimal and Not-Minimal K-Map Groupings CD CD F = C + CD + C + CD F = D + C + CD + C + CD Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

20 -45 ppendix Digital Logic Fig.45 The Corners of a K-Map re Logically djacent CD F = CD + D + Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

21 -46 ppendix Digital Logic.46 Two Different Minimized Equations re Produced from the Same K-Map CD CD d d d d F = CD + D F = D + D Computer Systems Design and rchitecture by V. Heuring and H. Jordan 997 V. Heuring and H. Jordan

22 -2 Notation Used at Circuit Intersections Connection No connection Connection No connection 999 M. Murdocca and V. Heuring

23 -2 OR-ND Implementation of Majority C + + C + + C F + + C + + C 999 M. Murdocca and V. Heuring

24 Data Inputs -27 Multiplexer D D D 2 D 3 F F D D D 2 D 3 Control Inputs F = D + D + D 2 + D M. Murdocca and V. Heuring

25 -28 ND-OR Implementation of MUX D D D 2 F D M. Murdocca and V. Heuring

26 -29 MUX Implementation of Majority Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs. C M F C 999 M. Murdocca and V. Heuring

27 -3 4-to- MUX Implements 3-Var Function Principle: Use the and inputs to select a pair of minterms. The value applied to the MUX data input is selected from {,, C, C} to achieve the desired behavior of the minterm pair. C F C C C C F 999 M. Murdocca and V. Heuring

28 -3 Demultiplexer D F = D F = D F F F 2 F 3 F 2 = D F 3 = D D F F F 2 F M. Murdocca and V. Heuring

29 -32 Gate-Level Implementation of DEMUX F D F F 2 F M. Murdocca and V. Heuring

30 -33 Decoder Enable = Enable = D D Enable D 2 D 3 D D D 2 D 3 D D D 2 D 3 D = D = D 2 = D3 = 999 M. Murdocca and V. Heuring

31 -34 Gate-Level Implementation of Decoder D D D 2 D 3 Enable 999 M. Murdocca and V. Heuring

32 -35 Decoder Implementation of Majority Function Note that the enable input is not always present. We use it when discussing decoders for memory. C M 999 M. Murdocca and V. Heuring

33 -36 Priority Encoder n encoder translates a set of inputs into a binary encoding. Can be thought of as the converse of a decoder. priority encoder imposes an order on the inputs. i has a higher priority than i+ 2 3 F F 2 3 F F F = F = M. Murdocca and V. Heuring

34 -37 ND-OR Implementation of Priority Encoder F 2 3 F 999 M. Murdocca and V. Heuring

35 -4 Example: Ripple-Carry ddition Carry In Operand Operand Carry Out Sum Carry Operand Example: Operand Sum M. Murdocca and V. Heuring

36 -4 Full dder i i C i S i C i+ i i C i+ Full adder S i C i 999 M. Murdocca and V. Heuring

37 -42 Four-it Ripple-Carry dder Four full adders connected in a ripple-carry chain form a four-bit ripple-carry adder. b 3 a 3 b 2 a 2 b a b a c 3 c 2 c c Full adder Full adder Full adder Full adder c 4 s 3 s 2 s s 999 M. Murdocca and V. Heuring

38 -44 Sequential Logic The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. There is a need for circuits with memory, which behave differently depending upon their previous state. n example is a vending machine, which must remember how many and what kinds of coins have been inserted. The machine should behave according to not only the current coin inserted, but also upon how many and what kinds of coins have been inserted previously. These are referred to as finite state machines, because they can have at most a finite number of states. 999 M. Murdocca and V. Heuring

39 -45 Classical Model of a Finite State n FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information. Inputs Machine i o i k Combinational logic unit D... n D n... s Synchronization n signal Delay elements (one per state bit) s... f o f m Outputs State bits 999 M. Murdocca and V. Heuring

40 -46 NOR Gate with Lumped Delay τ + + Timing ehavior The delay between input and output (which is lumped at the output for the purpose of analysis) is at the basis of the functioning of an important memory element, the flip-flop. τ 999 M. Murdocca and V. Heuring

41 -47 S-R Flip-Flop The S-R flip-flop is an active high (positive logic) device. t S t R t i+ S S R (disallowed) (disallowed) R τ 2 τ τ 2 τ Timing ehavior 999 M. Murdocca and V. Heuring

42 -48 NND Implementation of S-R Flip-Flop S S S R R R R S 999 M. Murdocca and V. Heuring

43 -5 Scientific Prefixes For computer memory, K = 2 = 24. For everything else, like clock speeds, K =, and likewise for M, G, etc. Prefix bbrev. uantity milli m micro µ nano n pico p Prefix bbrev. uantity Kilo K Mega M Giga G Tera T femto f 5 Peta P 5 atto a 8 Exa E M. Murdocca and V. Heuring

44 -52 Clocked S-R Flip-Flop S S R CLK CLK R τ 2 τ Timing ehavior The clock signal, CLK, enables the S and R inputs to the flip-flop. 999 M. Murdocca and V. Heuring

45 -53 Clocked D Flip-Flop The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop (next slide) addresses this problem. D CLK Circuit D CLK Symbol D C τ 2 τ 2 τ Timing ehavior τ 999 M. Murdocca and V. Heuring

46 -59 Example: Modulo-4 Counter Counter has a clock input (CLK) and a RESET input. Counter has two output lines, which take on values of,,, and on subsequent clock cycles. Time (t) RESET q Time (t) 3-bit q Synchronous s Counter D CLK s D s s 999 M. Murdocca and V. Heuring

47 -6 State Transition Diagram for RESET Output state / q q / / Output state Mod-4 Counter / / / / C / D Output state Output state 999 M. Murdocca and V. Heuring

48 -6 State Table for Mod-4 Counter Present state Input RESET / / C/ / C D/ / D / / Next state Output 999 M. Murdocca and V. Heuring

49 -62 State ssignment for Mod-4 Counter Present state (S t ) Input RESET : / / : / / C: / / D: / / 999 M. Murdocca and V. Heuring

50 -63 Truth Table for Mod-4 Counter RESET r(t) s (t) s (t) s s (t+) q q (t+) s (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) s (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) q (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) q (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) 999 M. Murdocca and V. Heuring

51 -64 Logic Design for Mod-4 Counter RESET CLK D s q D s q 999 M. Murdocca and V. Heuring

52 -67 Sequence Detector State Table Present state Input X / C/ D/ E/ C F/ G/ D D/ E/ E F/ G/ F D/ E/ G F/ G/ 999 M. Murdocca and V. Heuring

53 -68 Sequence Detector State ssignment Input and state at time t Next state and output at time t+ Present state Input X S 2 S S S 2 S S Z S 2 S S Z : / / : / / C: / / D: / / E: / / F: / / G: / / (a) s 2 s s x s 2 d d s d d s d d z d d (b) 999 M. Murdocca and V. Heuring

54 -69 Sequence Detector Logic Diagram x x x D S 2 x x x x x x x D S x x x x x x x D S x x x Z CLK 999 M. Murdocca and V. Heuring

55 -75 Four-it Register Makes use of tri-state buffers so that multiple registers can gang their outputs to common output lines. D 3 D 2 D D Write (WR) CLK D D D D Enable (EN) WR D 3 D 2 D D 3 2 EN M. Murdocca and V. Heuring

56 -77 Modulo-8 Counter Note the use of the T flip-flops, implemented as J-K s. They are used to toggle the input of the next flip-flop when its output is. CLK Enable (EN) J K J K J K RESET 2 CLK ENLE RESET MOD(8) COUNTER 2 2 Timing ehavior 999 M. Murdocca and V. Heuring

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring - Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties