CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing

2 Mux, Demux Encoder, Decoder 2

3 Transmission Gate: Mux/Tristate building block nmos are on when gate= pass s poorly from source to drain pmos are on when gate= pass s poorly from source to drain Transmission gate is a better switch passes both and well When EN =, the switch is ON: EN = and A is connected to B When EN =, the switch is OFF: A is not connected to B A EN EN B

4 shared bus Floating: Z, Tristate Buffer and Tristate Busses Floating, high impedance, open, high Z Disconnected Floating nodes are used in tristate busses many different drivers, but only one is active at once Tristate Bus processor to bus from bus en Tristate Buffer video en2 E to bus from bus A Y Ethernet en3 to bus E A Y Z Z from bus memory to bus from bus en4

5 2: Multiplexer or Mux Selects between one of N inputs to connect to output log 2 N-bit select input control input Example: 2: Mux D D S Y Logic gates Tristates Pass gates Y D D S D S Y S D D Y S Y D D D S D Y = D S + D S D Y

6 2: mux: Z = A'I + AI Multiplexers 4: mux: Z = A'B'I + A'BI + AB'I 2 + ABI 3 8: mux: Z = A'B'C'I + A'B'CI + A'BC'I 2 + A'BCI 3 + AB'C'I 4 + AB'CI 5 + ABC'I 6 + ABCI 7 In general: Z = 2 n -(m k I k ) k= in minterm shorthand form for a 2 n : Mux I I 2: mux A Z I I I2 I3 4: mux A B Z I I I2 I3 I4 I5 I6 I7 8: mux A B C Z 6

7 Logic using Multiplexers Example of 2: mux implementation Y = AB A B Y A Y A B B Y

8 Logic using Multiplexers This multiplexer implements the same functionality for Y as the truth table A. Yes B. No A B Y Y = AB GND Vdd A B Y

9 Mux as general-purpose logic Example: Z(A,B,C) = AC + BC' + A'B C I I I2 I : mux Z A B 9

10 Cascading muxes I I C 2: mux I Z I C 2: mux Z A B A Function Z(A,B,C) implemented by 2: Muxes above is: A. A B C +ABC+BC B. (A +AC)B+B C C. A B +B C+BC D. A +AC+BC E. None of the above

11 Mux example: Logical function unit C C C2 Function Comments always A + B logical OR (A B)' logical NAND A xor B logical xor A xnor B logical xnor A B logical AND (A + B)' logical NOR always 2 3 8: MUX S2 S S F C C C2

12 Multiplexer En D D D 2 D y What is the output of the mux if En=, S= 2, D[3:]=A 6? A. B. C.Z D.X E.None of the above S S Selects between one of N inputs to connect to the output. log 2 N-bit select input control input

13 Demultiplexers (opposite of Mux) En y i = x if i = (S n-,.., S ) & En = y i = otherwise x y 2 n- -y S(n-,) Control Input 3

14 Decoder N inputs, 2 N outputs One-hot outputs: only one output HIGH at a time when enable signal is (EN=) EN A A 2:4 Decoder Y 3 Y 2 Y Y A A Y 3 Y 2 Y Y

15 Decoder: logic equations & implementation Decoders/demultiplexers control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable or G in equations-> :2 Decoder: O = G S O = G S A A EN 2:4 Decoder: O = G S S O = G S S O2 = G S S O3 = G S S Y 3 Y 2 Y Y 3:8 Decoder: O = G S2 S S O = G S2 S S O2 = G S2 S S O3 = G S2 S S O4 = G S2 S S O5 = G S2 S S O6 = G S2 S S O7 = G S2 S S

16 Logic Using Decoders OR minterms EN A B 2:4 Decoder Minterm AB AB AB AB EN 2 3 3:8 DEC S2 S S A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC Y = AB + AB = A B Y A B C

17 F(A,B,C) = M(,2,4) Another example 7

18 Example as general-purpose logic F = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A' + B' + C' + D') Enable 4:6 DEC A'B'C'D' A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D AB'CD' AB'CD 2 ABC'D' 3 ABC'D 4 ABCD' 5 ABCD A B C D

19 Decoder Applications Decoder converts a binary address to the assertion of the addressed device I I I 2 2 E (enable) y y.. y 7 n to 2 n decoder function: y i = if E= & (I 2, I, I ) = i y i = otherwise n inputs n= 3 2 n outputs 2 3 = 8 9

20 Tree of Decoders En Implement a decoder with decoders. En y I 2, I, I D y 7 I 5, I 4, I 3 I 2, I, I D y 8 y 5 y 56 I 2, I, I D7 y 63 2

21 Encoder En I 3 8 inputs 3 outputs I A 2 y y y 2 At most one I i =. (y n-,.., y ) = i if I i = & En = (y n-,.., y ) = otherwise. A = if En = and one i s.t. I i = A = otherwise.

22 Encoder: Logic Diagram En En y y I I 3 I 5 I 7 En I 2 I 3 I 6 I 7 En y 2 I 4 I 5 I 6 I 7 I I.. I 6 I 7 A 22

23 Decoder, Encoder, Mux, Demux Processors P Data Mux Arbiter Memory Bank Address Data P2 Address 2 Address k Pk Demux Mux Data k Address n n-m Decoder Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals m 2 m 23

24 Adders 24

25 -Bit & Multi-bit Adders Half Adder A B Full Adder A B Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) C out + A B S C out S = A B C out = AB S C in C out + S A B C out C in S C out Symbol A B N N + S N C in S = A B C in C out = AB + AC in + BC in

26 Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: A B late @ two gate delays to compute Cout A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 Ripple-carry adder delay S S t ripple = Nt FA where t FA is the delay of a full adder

27 Carry-lookahead adders Adder with propagate (P) and generate (G) outputs: Evaluate Sum and Ci+ Sum = Ai xor Bi xor Ci Ci+ = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi Ai Bi Ci gate delay 2 gate delays gate delay increasingly complex logic for carries C P G C P P G P G 3 3 C P P P2 G P P2 G P2 G2 3 C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 G3 3 27

28 Carry-Lookahead Adder Example: 4-bit blocks (G 3: and P 3: ) : Generally: G 3: = G 3 + P 3 (G 2 + P 2 (G + P G ) P 3: = P 3 P 2 P P Step : Compute G i and P i for all columns Step 2: Compute G and P for k-bit blocks Step 3: C in propagates through each k-bit propagate/generate block G i:j = G i + P i (G i- + P i- (G i-2 + P i-2 G j ) P i:j = P i P i- P i-2 P j C i = G i:j + P i:j C i-

29 Adders: CLA vs. Ripple You are designing a 64-bit adder. To get the best performance, would you design: A. A 64-bit ripple-carry adder B. A 64-bit carry-lookahead adder C. 8-bit sections of carry-lookahead with ripple carry connecting them D. 32-bit sections of ripple-carry connected with carrylookahead 29

30 Subtractors 3

31 2s complement If N is a positive number, then the negative of N (its 2s complement or N* ) is bit-wise complement plus 7* is -7 : -> + = (-7) -7* is 7: -> + = ( 7)

32 Subtraction If you are using 4 bit number, what is the result of the following equation in 2s complement: y = 4-7 A. B. C. D. E. None of the above 32

33 Detecting Overflow: Method Assuming 4-bit two s complement numbers, one can detect overflow by detecting when the two numbers sign bits are the same but are different from the result s sign bit If the two numbers sign bits are different, overflow is impossible Adding a positive and negative can t exceed the largest magnitude positive or negative Simple circuit overflow = a3 b3 s3 + a3b3s3 sign bits overflow (a) overflow (b) no overflow (c) If the numbers sign bits have the same value, which differs from the result s sign bit, overflow has occurred. 33

34 Detecting Overflow: Method 2 Detect a difference between carry-in to sign bit and carry-out from it Yields a simpler circuit: overflow = c3 xor c4 = c3 c4 + c3 c overflow (a) overflow (b) no overflow (c) If the carry into the sign bit column differs from the carry out of that column, overflow has occurred. 34

35 Subtractor Symbol A B N N - Y N Implementation A B N N N + Y N

36 Adder/subtractor A3 B3B3' A2 B2B2' A BB' A BB' Sel Sel Sel Sel A B A B A B A B Cout Cin Cout Cin Cout Cin Cout Cin Sel Sum Sum Sum Sum S3 S2 S S Overflow In this schematic addition occurs when Sel signal is: A. True B. False 36

37 More ALU Components 37

38 Comparator: Equality Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A Equal Equal B A B

39 Comparator: Less Than A N B N - N [N-] A < B 5-<39>

40 Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 =

41 General Shifter Design A 3 A 2 A A shamt : 2 S : Y 3 shamt : 2 S : Y A 3: >> Y 3: S : Y S : Y

42 Multiplication of positive binary numbers Generalized representation of multiplication by hand For demo see: 42

43 pp4 pp3 pp2 pp Multiplier design array of AND gates Multiplier Array Style a3 a2 a a b b b2 + (5-bit) b3 + (6-bit) A * P B + (7-bit) Block symbol p7..p 43

44 Division of positive binary numbers Repeated subtraction Set quotient to Repeat while dividend >= divisor Subtract divisor from dividend Add to quotient When dividend < divisor: Reminder = dividend Quotient is correct Example: Dividend: ; Divisor: Dividend Quotient For demo see: 44

45 ALU: Arithmetic Logic Unit 46

46 Designing an Arithmetic Logic Unit ALUop 3 A N Zero B N ALU N CarryOut Result Overflow ALU Control Lines (ALUop) Function And Or Add Subtract Set-on-less-than 47

47 A One Bit ALU This -bit ALU performs AND, OR, and ADD

48 -bit ALU A 32-bit ALU 32-bit ALU 49

49 Subtract We d like to implement a means of doing A-B (subtract) but with only minor changes to our hardware. How?. Provide an option to use bitwise NOT A 2. Provide an option to use bitwise NOT B 3. Provide an option to use bitwise A XOR B 4. Provide an option to use instead of the first CarryIn 5. Provide an option to use instead of the first CarryIn Selection A Choices alone B Both and 2 C Both 3 and 4 D Both 2 and 5 E None of the above 5

50 Full 32-bit ALU what signals accomplish ADD? Binvert CIn Oper A 2 B 2 C 2 D 2 E NONE OF THE ABOVE sign bit (adder output from bit 3) 5

51 Full 32-bit ALU what signals accomplish OR? Binvert CIn Oper A B C D E NONE OF THE ABOVE sign bit (adder output from bit 3) 52

52 Full 32-bit ALU Little more intense can you get this? what signals accomplish SUB? Binvert CIn Oper A 2 B 2 C 2 D 2 E NONE OF THE ABOVE sign bit (adder output from bit 3) 53

53 Zero Extend 2 3 Arithmetic Logic Unit Example 2 A N N N B N F 2 A N ALU N Y B N 3 F F 2: Function A & B A B A + B Not used A & ~B A ~B C out + [N-] S A - B Not used N N N N 2 F : Y N

54 ALU Design Example 3 S2 S S Function B-A A-B A+B A xor B A or B A and B 55