CMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

Transcription

1 CMSC 33 Lecture 5 Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang <chang@umbc.edu>

2 Good-bye ssembly Language What a pain! Understand pointers better Execution environment of Unix processes the stack virtual memory Linking & loading UMC, CMSC33, Richard Chang <chang@umbc.edu>

3 -3 ppendix : Digital Logic Some Definitions Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder. Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit. Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

4 -4 ppendix : Digital Logic The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, and, and, or 5 V and V for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. set of inputs i i n are presented to the CLU, which produces a set of outputs according to mapping functions f f m. i i i n... Combinational logic unit... f (i, i ) f (i, i 3, i 4 ) f m (i 9, i n ) Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

5 3-6 Ripple Carry dder Chapter 3: rithmetic Two binary numbers and are added from right to left, creating a sum and a carry at the outputs of each full adder for each bit position. b 3 a 3 c 3 b 2 a 2 c 2 b a c b a c Full adder Full adder Full adder Full adder c 4 s 3 s 2 s s Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

6 -45 ppendix : Digital Logic Classical Model of a Finite State n FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information. Inputs Machine i o i k Combinational logic unit Q D... Q n D n... s Synchronization n signal Delay elements (one per state bit) s... f o f m Outputs State bits Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

7 -7 ppendix : Digital Logic Vending Machine State Transition Q/ dime is inserted Diagram / = Dispense/Do not dispense merchandise N/ D/ / = Return/Do not return a nickel in change / = Return/Do not return a dime in change N/ D Q/ D/ 5 5 Q/ Q/ D/ Principles of Computer rchitecture by M. Murdocca and V. Heuring D/ N/ C N/ N = Nickel D = Dime Q = Quarter 999 M. Murdocca and V. Heuring

8 CMSC 33, Computer Organization & ssembly Language Programming, Section Fall 23 Course Syllabus We will follow two textbooks: Principles of Computer rchitecture, by Murdocca and Heuring, and Linux ssembly Language Programming, by Neveln. The following schedule outlines the material to be covered during the semester and specifies the corresponding sections in each textbook. Date Topic M&H Neveln ssign Due Th 8/28 Introduction & Overview Tu 9/2 Data Representation I , , hw Th 9/4 Data Representation II Tu 9/9 i386 ssembly Language I , hw2, proj hw Th 9/ i386 ssembly Language II Tu 9/6 i386 ssembly Language III proj2 hw2, proj Th 9/8 i386 ssembly Language IV Tu 9/23 Examples proj3 proj2 Th 9/25 Machine Language Tu 9/3 Compiling, ssembling & Linking Th /2 Subroutines Tu /7 The Stack & C Functions proj4 proj3 Th /9 Linux Memory Model Tu /4 Interrupts & System Calls proj4 Th /6 Midterm Exam Tu /2 Introduction to Digital Logic Th /23 Transistors & Logic Gates.3-.4 hw3 Tu /28 In-class Lab I Th /3 oolean Functions & Truth Tables.5-.9 hw4 hw3 Tu /4 Circuits for ddition 3.5 Th /6 Circuit Simplification I.-.2 hw5 hw4 Tu / Combinational Logic Components. Th /3 Flip Flops. digsim hw5 Tu /8 In-class Lab II Th /2 Finite State Machines.2-.5 Tu /25 Circuit Simplification II.3 digsim Th /27 Thanksgiving break Tu 2/2 Finite State Machine Design digsim2 Th 2/4 More Finite State Machine Design Tu 2/9 I/O & Memory , digsim2 Tu 2/6 Final Exam :3am-2:3pm

9 -5 ppendix : Digital Logic Truth Table Developed in 854 by George oole. Further developed by Claude Shannon (ell Labs). Outputs are computed for all possible input combinations (how many input combinations are there?) Consider a room with two light switches. How must they work? GND Inputs Output Hot Light Z Z Switch Switch Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

10 -6 ppendix : Digital Logic lternate ssignment of Outputs to Switch Settings We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior. Inputs Output Z Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

11 -7 ppendix : Digital Logic Truth Tables Showing ll Possible Functions of Two inary Variables Inputs Outputs The more frequently used functions have names: ND, XOR, OR, NOR, XOR, and NND. (lways use upper case spelling.) False ND XOR OR Inputs Outputs NOR XNOR + + NND True Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

12 -8 ppendix : Digital Logic Logic Gates and Their Symbols Logic symbols shown for ND, OR, buffer, and NOT oolean functions. F F Note the use of the inversion bubble. F = F = + (e careful about the nose of the gate when drawing ND vs. OR.) ND F OR F F = F = uffer NOT (Inverter) Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

13 ppendix : Digital Logic -9 Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring Logic Gates and their Symbols (cont ) F NND F NOR F = F = + F Exclusive-OR (XOR) F = F Exclusive-NOR (XNOR) F =.

14 - ppendix : Digital Logic Variations of Logic Gate Symbols C F = C F = + (a) (b) + + (c) (a) 3 inputs (b) Negated input (c) Complementary outputs Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

15 -4 ppendix : Digital Logic Tri-State uffers Outputs can be,, or electrically disconnected. C F ø ø C F ø ø C F = C or F = ø C F = C or F = ø Tri-state buffer Tri-state buffer, inverted control Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

16 -8 ppendix : Digital Logic Sum-of-Products Form: The Majority Function The SOP form for the 3-input majority function is: M = C + C + C + C = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7). Each of the 2 n terms are called minterms, ranging from to 2 n -. Note relationship between minterm number and boolean value. Minterm Index C F -side -side balance tips to the left or right depending on whether there are more s or s. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

17 -9 ppendix : Digital Logic ND-OR Implementation of Majority C Gate count is 8, gate input count is 9. C C F C C Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

18 -2 ppendix : Digital Logic Notation Used at Circuit Intersections Connection No connection Connection No connection Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

19 Sum of Products (a.k.a. disjunctive normal form) OR (i.e., sum) together rows with output ND (i.e., product) of variables represents each row e.g., in row 3 when x = ND x 2 = ND x 3 = or when x x 2 x 3 = MJ3(x, x 2, x 3 ) = x x 2 x 3 +x x 2 x 3 +x x 2 x 3 +x x 2 x 3 = m(3, 5, 6, 7) x x 2 x 3 MJ

20 Product of Sums (a.k.a. conjunctive normal form) ND (i.e., product) of rows with output OR (i.e., sum) of variables represents negation of each row e.g., NOT in row 2 when x = OR x 2 = OR x 3 = or when x + x 2 + x 3 = MJ3(x, x 2, x 3 ) = (x +x 2 +x 3 )(x +x 2 +x 3 )(x +x 2 +x 3 )(x +x 2 +x 3 ) = M(,, 2, 4) x x 2 x 3 MJ

21 -2 ppendix : Digital Logic OR-ND Implementation of Majority C + + C + + C F + + C + + C Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

22 Equivalences Every oolean function can be written as a truth table Every truth table can be written as a oolean formula (SOP or POS) Every oolean formula can be converted into a combinational circuit Every combinational circuit is a oolean function Later you might learn other equivalencies: finite automata regular expressions computable functions programs 3

23 Universality Every oolean function can be written as a oolean formula using ND, OR and NOT operators. Every oolean function can be implemented as a combinational circuit using ND, OR and NOT gates. Since ND, OR and NOT gates can be constructed from NND gates, NND gates are universal. 4

24 -7 ppendix : Digital Logic ll-nnd Implementation of OR NND alone implements all other oolean logic gates. + + Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

25 -6 ppendix : Digital Logic DeMorgan s Theorem = = + + DeMorgan s theorem: + = + = F = + F = Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring

26 DigSim Java applet/application that simulates digital logic Not for industrial use, good enough for us dvantages: FREE, runs on most platforms Disadvantages: slow, timing issues, saving issues UMC, CMSC33, Richard Chang

27 CMSC 33, Computer Organization & ssembly Language Programming Section Spring 22 DigSim ssignment 3: J-K Flip-Flops Due: Tuesday May 4, 22 Objective The objective of this assignment is to implement a finite state machine using J-K flip-flops. ssignment Consider the following transition diagram (from Contemporary Logic Design, Randy H. Katz, enjamin-cummings Publishing, 994) for a finite state machine with input bit and output bit: / S / / S / S 2 / / / / S 3 / S 4 / / S 5 / Your assignment is to implement this finite state machine using J-K flip flops. ssume that the state assignments are for S, for S, S 2, for S 3, for S 4, and for S 5.. In the truth table on the next page, let, and C be the current states and, and C be the next states stored in the J-K flip flops. (E.g., S 4 is assigned =, = and C=.) We also use D for the bit input. Fill in the rest of the truth table using the excitation table for J-K flip flops. For example, in row 9, flip-flop is currently storing and must store in the next state. To achieve this, we look at the entry of the excitation table and note that the J input to flip-flop (call it J) can be set to anything, but the K input, K, must be set to. 2. Use the Karnaugh maps provided to simplify the oolean formulas for the J and K inputs to each J-K flip flop and for the output value z. 3. Implement the resulting circuit in DigSim.

28 Transistors & Gates Next time UMC, CMSC33, Richard Chang