CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati

2 Definition of terms for two-level simplification ON-set: the set of all s in the result of a logic function (i.e. all boxes of a Kmap where the value is ) OFF-set: the set of all s in the result of a logic function (i.e. all boxes of a Kmap where the value is ) SOP: Sum of Products Canonical SOP = minterms expansion Minimal SOP = resulting from 2-level minimization (i.e. Kmaps) by covering s Similar definitions for POS 2

3 Definition of terms for two-level simplification Implicant single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube Prime implicant implicant that can't be combined with another to form a larger subcube Essential prime implicant prime implicant is essential if it alone covers an element of ON-set will participate in LL possible covers of the ON-set DC-set used to form prime implicants but not to make implicant essential Cover: a subset of implicants that covers all s in the Kmap Objective: grow implicant into prime implicants (minimize literals per term) cover the ON-set with as few prime implicants as possible (minimize number of product terms) 3

4 Examples to illustrate terms X D C B D C B 4

5 Examples to illustrate terms X D 6 prime implicants: 'B'D, BC', C, 'C'D, B, B'CD essential C minimum cover: C + BC' + 'B'D B 5 prime implicants: BD, BC', CD, 'BC, 'C'D D essential minimum cover: 4 essential implicants C B 5

6 C B D C X B X D How many essential Prime implicants?. B. C. 2 D. 3 6

7 lgorithm for two-level simplification (example) X X X C X B X D D X X C B 2 primes around 'BC'D' D X X C B 2 primes around BC'D X X X D D D X X C B 3 primes around B'C'D' C X X B 2 essential primes X X C B minimum cover (3 primes) 7

8 Essential primes How many essential Prime implicant?. B. C. 2 D. 3 E. None of the above C X X X B X X D For more practice: think about essential prime implicates! 8

9 CSE4: Components and Design Techniques for Digital Systems Muxes and demuxes 9

10 Multiplexer (Example) Four possible display items Temperature (T), verage miles-per-gallon (), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide Choose which to display using two inputs x and y Use 8-bit 4x mux

11 Multiplexer (Example) You are not sure whether an input of the MUX would have a or a You should build the MUX with a component that is good at passing both s and s

12 Transmission Gate: Mux/Tristate building block nmos are on when gate= good at passing s from source to drain pass s poorly from source to drain pmos are on when gate= - good at passing s from source to drain pass s poorly from source to drain Transmission gate is a better switch passes both and well When EN =, the switch is ON: EN = and is connected to B When EN =, the switch is OFF: is not connected to B The pass transistor acts as a tristate buffer EN B EN

13 Floating: Z, Tristate Buffer and Tristate Busses Floating, high impedance, open, high Z Disconnected Floating nodes are used in tristate busses many different drivers, but only one is active at once Tristate Bus processor to bus from bus en Tristate Buffer video en2 E Y to bus from bus Ethernet to bus en3 shared bus E Y Z Z Note: do not confuse this with the inverter symbol! from bus memory to bus from bus en4

14 2: Multiplexer or Mux Selects between one of N inputs to connect to output log 2 N-bit select input control input Example: 2: Mux Pass gates Tristates S S D D S Y Logic gates Y D D S S D D S D D Y S D D Y S Y D D D S D Y = D S + D S Y

15 Multiplexers/selectors 2: mux: Z = 'I + I 4: mux: Z = 'B'I + 'BI + B'I 2 + BI 3 8: mux: Z = 'B'C'I + 'B'CI + 'BC'I 2 + 'BCI 3 + B'C'I 4 + B'CI 5 + BC'I 6 + BCI 7 In general: shorthand form for a 2 n : Mux I I 2: mux Z I I I2 I3 For example 4: mux B Z I I I2 I3 I4 I5 I6 I7 8: mux B C Z 5

16 Logic using Multiplexers Example of 2: mux implementation Y = B B Y Y B B Y You can implement a 2-variables logic function using a 2: multiplexer: - Use one variable for the selection input - Connect the MUX inputs to either - The second variable (in true or complemented form) - GND - VDD - You can also use larger MUXs (see next slide)

17 Logic using Multiplexers This multiplexer implements the same functionality for Y as the truth table. Yes B. No B Y Y = B GND Vdd B Y

18 Mux as general-purpose logic Example: Z(,B,C) = C + BC' + 'B C I I I2 I : mux Z B 8

19 Cascading muxes I I C 2: mux I Z I C 2: mux Z B Function Z(,B,C) implemented by 2: Muxes above is:. B C +BC+BC B. ( +C)B+B C C. B +B C+BC D. ( +C)B +BC E. None of the above

20 Mux example: Logical function unit C C C2 Function Comments always + B logical OR ( B)' logical NND xor B logical xor xnor B logical xnor B logical ND ( + B)' logical NOR always 2 3 8: MUX S2 S S F C C C2 2

21 Demux or Decoder N inputs, 2 N outputs One-hot outputs: only one output HIGH at a time when enable signal is (EN=) EN 2:4 Decoder Y 3 Y 2 Y Y For the moment, we call it decoder or demuxer with no distinction. We ll see the (slight) difference later Y 3 Y 2 Y Y

22 Decoder: logic equations & implementation Decoders/demultiplexers control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable or G in equations-> :2 Decoder: O = G S O = G S EN 2:4 Decoder: O = G S S O = G S S O2 = G S S O3 = G S S Y 3 Y 2 Y Y 3:8 Decoder: O = G S2 S S O = G S2 S S O2 = G S2 S S O3 = G S2 S S O4 = G S2 S S O5 = G S2 S S O6 = G S2 S S O7 = G S2 S S

23 Function using Decoder EN 2 3 3:8 DEC S2 S S 'B'C' 'B'C 'BC' 'BC B'C' B'C BC' BC B C Example: = (3,4,7) 23

24 Logic Using Decoders OR minterms EN B 2:4 Decoder Minterm B B B B EN 2 3 3:8 DEC S2 S S 'B'C' 'B'C 'BC' 'BC B'C' B'C BC' BC Y = B + B = B Y B C

25 Example of demux as general-purpose logic F = 'BC'D + 'B'CD + BCD F2 = BC'D' + BC F3 = (' + B' + C' + D') Enable 4:6 DEC 'B'C'D' 'B'C'D 2 'B'CD' 3 'B'CD 4 'BC'D' 5 'BC'D 6 'BCD' 7 'BCD 8 B'C'D' 9 B'C'D B'CD' B'CD 2 BC'D' 3 BC'D 4 BCD' 5 BCD F F2 F3 B C D

26 F(,B,C) = M(,2,4) nother example 26

27 nother example Implement this function using -2 and 2-4 decoders. F(,B,C) = M(,2,4) 27

28 Tree of Decoders En Implement a decoder with decoders. En y I 2, I, I D y 7 I 5, I 4, I 3 I 2, I, I D y 8 y 5 y 56 You can use smaller decoders to build a larger one I 2, I, I D7 y 63 28

29 Multi-level logic x = D F + E F + B D F + B E F + C D F + C E F + G reduced sum-of-products form already simplified 6 x 3-input ND gates + x 7-input OR gate (that may not even exist!) 25 wires (9 literals plus 6 internal wires) x = ( + B + C) (D + E) F + G factored form not written as two-level S-o-P x 3-input OR gate, 2 x 2-input OR gates, x 3-input ND gate wires (7 literals plus 3 internal wires) B C X D E F G

30 Multi-level logic No global definition of optimal multilevel circuit Optimality depends on user-defined goals Synthesize an implementation that meets design goals Synthesis requires CD-tool help No simple hand methods like K-maps CD tools manipulate Boolean expressions Factoring, decomposition, etc dvantages over 2-level logic Smaller circuits Reduced fan-in Less wires Disadvantages w.r.t 2-level logic More difficult design Less powerful optimizing tools Dynamic hazards

31 Demultiplexer and Decoder - Demultiplexer: has a data input and it reports it on the output line specified by the selection - Decoder: takes an input address and switches to the corresponding output line - Note: the behavior of a decoder with enable would be the same of a demultiplexer, but we give different names to the inputs Enable inputs Decoder outputs input Demultiplexer outputs Selection 3

32 CSE4: Components and Design Techniques for Digital Systems dders, subtractors comparators, multipliers and other LU elements 32

33 dders 33

34 Circuit Delay Transistors have instrinsic resistance and capacitance Signals take time to propagate from the input to the output of a gate Sometimes delays are labeled in circuit drawings 34

35 -Bit & Multi-bit dders Half dder C out + S B C out Full dder + S B C in Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) Two-level logic adder (even faster) B C out S = B C out = B S C in B C out S C out Symbol B N N + S N C in S = B C in C out = B + C in + BC in

36 Ripple-Carry dder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow 3 B 3 3 B 3 B B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Ripple-carry adder delay t ripple = Nt F where t F is the delay of a full adder

37 Two-level Logic dder No matter how many inputs you have, look at the truth table, convert to Kmap, apply the algorithm for two-level logic minimization Very fast adder, but. Beyond 8 inputs, a shockingly large amount of gates! Number of gates increases exponentially Ripple carry adder Carry-lookahead adder (next slide) FST Two-level logic adder COMPLEX

38 Carry-lookahead adders c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s Carries First operand Second operand From the very beginning I can look ahead into the value of carries

39 Full dder Ci+ = i Bi + Ci (i xor Bi) Generate Propagate Ci+ = Gi + Ci Pi 39

40 Carry-lookahead adders dder with propagate (P) and generate (G) outputs: Ci+ = i Bi + Ci (i xor Bi) Generate Propagate Ci+ = Gi + Ci Pi The carry at some level is equal to if either the generate signal is equal to one or if the propagate and the previous carry are both

41 Carry-lookahead adders Example: 4-bit CL adder c = G + P c c2 = G + P c c3 = G2 + P2 c2 c4 = G3 + P3 c3 Gi = ai bi Pi = ai xor bi generate propagate ll G and P are immediately available, but c are not (except the c). So you need to make substitutions: c = G + P c c2 = G + P (G + P c) c3 = G2 + P2 c2 c4 = G3 + P3 c3 = G + PG + PPc = (derive at home) = (derive at home) 4

42 Carry-lookahead adders Propagate/Generate circuit (one per each input bit) i Bi Ci gate delay 2 gate delays gate delay Carry circuits (implement the equations derived in the previous slide) C P G C P P G P G 3 3 C P P P2 G P P2 G P2 G2 3 Note: this approach of looking ahead for building multi-bit operations is not limited to adders! C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 G3 3 42

43 Combining dders Example: connect CLs in a ripple-carry style (6-bit adder) 4-bit 4-bit 4-bit 4-bit CL CL CL cout CL Example: connect ripple-carry in CL style (4-bit adder) B[3:2] [3:2] S[5:2] S[:8] S[7:4] S[3:] CL logic B[:] [:] c2 Ripplecarry 2-bit S[3:2] Ripplecarry 2-bit S[:] c Connect carries in a chain cin c2 = G + PG + PPc Where: G = B G = B P = xor B P = xor B 43