CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification

Transcription

1 CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang <chang@umbc.edu>

2 CMSC 33, Computer Organization & ssembly Language Programming, section Fall 23 Homework 4 Due: Thursday, November 6, 23. ( points) Question 3.8, page 96, Murdocca & Heuring 2. ( points) Question 3.9, page 96, Murdocca & Heuring 3. (2 points) Read the instructions on how to run the DigSim digital simulator on the course web page: Using DigSim, wire up the following circuit diagram, play with the switches, create a text box with your name, and save the circuit diagram. (This is the same as the circuit we used in the in-class lab.) The file which has your circuit diagram should be a plain text file that starts with something like: # Digsim file version describe component TwoNandPort pos 23 3 Use a text editor to look at the file and make sure that the file is not empty and has some data similar to the above. Next, use DigSim to load the file and make sure that this still works. If all is well, submit the circuit file using the Unix submit command as in previous assignments. The submission name for this assignment is: digsim.the UNIX command to do this should look something like: submit cs33_ digsim xor.sim

3 Last Time & efore In-class lab: next time Tuesday /8 Half adders & full adders Ripple carry adders vs carry lookahead adders Propagation delay UMC, CMSC33, Richard Chang

4 -26 ppendix : Digital Logic Digital Components High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates. Levels of integration (numbers of gates) in an integrated circuit (IC) can roughly be considered as: Small scale integration (SSI): - gates. Medium scale integration (MSI): to gates. Large scale integration (LSI): -, logic gates. Very large scale integration (VLSI):,-upward logic gates. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. 999 M. Murdocca and V. Heuring

5 Data Inputs -27 ppendix : Digital Logic Multiplexer D D D 2 D 3 F F D D D 2 D 3 Control Inputs F = D + D + D 2 + D M. Murdocca and V. Heuring

6 -28 ppendix : Digital Logic ND-OR Implementation of MUX D D D 2 F D M. Murdocca and V. Heuring

7 -29 ppendix : Digital Logic MUX Implementation of Majority Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs. C M F C 999 M. Murdocca and V. Heuring

8 -3 ppendix : Digital Logic 4-to- MUX Implements 3-Var Function Principle: Use the and inputs to select a pair of minterms. The value applied to the MUX data input is selected from {,, C, C} to achieve the desired behavior of the minterm pair. C F C C C C F 999 M. Murdocca and V. Heuring

9 -3 ppendix : Digital Logic Demultiplexer D F = D F = D F F F 2 F 3 F 2 = D F 3 = D D F F F 2 F M. Murdocca and V. Heuring

10 -32 ppendix : Digital Logic Gate-Level Implementation of DEMUX F D F F 2 F M. Murdocca and V. Heuring

11 -33 ppendix : Digital Logic Decoder Enable = Enable = D D Enable D 2 D 3 D D D 2 D 3 D D D 2 D 3 D = D = D 2 = D3 = 999 M. Murdocca and V. Heuring

12 -34 ppendix : Digital Logic Gate-Level Implementation of Decoder D D D 2 D 3 Enable 999 M. Murdocca and V. Heuring

13 -35 ppendix : Digital Logic Decoder Implementation of Majority Function Note that the enable input is not always present. We use it when discussing decoders for memory. C M 999 M. Murdocca and V. Heuring

14 -36 Priority Encoder ppendix : Digital Logic n encoder translates a set of inputs into a binary encoding. Can be thought of as the converse of a decoder. priority encoder imposes an order on the inputs. i has a higher priority than i+ 2 3 F F 2 3 F F F = F = M. Murdocca and V. Heuring

15 -37 ppendix : Digital Logic ND-OR Implementation of Priority Encoder F 2 3 F 999 M. Murdocca and V. Heuring

16 -38 C ppendix : Digital Logic Programmable Logic rray OR matrix PL is a customizable ND matrix followed by a customizable OR matrix. lack box view of PL: C PL F F Fuses ND matrix F F 999 M. Murdocca and V. Heuring

17 -39 C ppendix : Digital Logic Simplified Representation of PL Implementation of Majority Function C C C C F (Majority) F (Unused) 999 M. Murdocca and V. Heuring

18 -4 ppendix : Digital Logic Full dder i i C i S i C i+ i i C i+ Full adder S i C i 999 M. Murdocca and V. Heuring

19 -43 C in ppendix : Digital Logic PL Realization of Full dder Sum C out 999 M. Murdocca and V. Heuring

20 -3 ppendix : Reduction of Digital Logic Reduction (Simplification) of oolean Expressions It is usually possible to simplify the canonical SOP (or POS) forms. smaller oolean equation generally translates to a lower gate count in the target circuit. We cover three methods: algebraic reduction, Karnaugh map reduction, and tabular (Quine-McCluskey) reduction. 999 M. Murdocca and V. Heuring

21 -7 ppendix : Reduction of Digital Logic Karnaugh Maps: Venn Diagram Representation of Majority Function Each distinct region in the Universe represents a minterm. This diagram can be transformed into a Karnaugh Map. C C C C C C C C C 999 M. Murdocca and V. Heuring

22 -8 ppendix : Reduction of Digital Logic K-Map for Majority Function Place a in each cell that corresponds to that minterm. Cells on the outer edge of the map wrap around Minterm Index C F C -side -side balance tips to the left or right depending on whether there are more s or s. 999 M. Murdocca and V. Heuring

23 -9 ppendix : Reduction of Digital Logic djacency Groupings for Majority Function C F = C + C M. Murdocca and V. Heuring

24 - ppendix : Reduction of Digital Logic Minimized ND-OR Majority Circuit C F F = C + C + The K-map approach yields the same minimal two-level form as the algebraic approach. 999 M. Murdocca and V. Heuring

25 - ppendix : Reduction of Digital Logic K-Map Groupings Minimal grouping is on the left, non-minimal (but logically equivalent) grouping is on the right. To obtain minimal grouping, create smallest groups first. CD CD F = C + C D + C + C D F = D + C + C D + C + C D 999 M. Murdocca and V. Heuring

26 Example Requiring More Rules CD D C UMC, CMSC33, Richard Chang <chang@umbc.edu>

27 -2 ppendix : Reduction of Digital Logic K-Map Corners are Logically djacent CD F = C D + D M. Murdocca and V. Heuring

28 -3 ppendix : Reduction of Digital Logic K-Maps and Don t Cares There can be more than one minimal grouping, as a result of don t cares. CD d CD d d d F = C D + D F = D + D 999 M. Murdocca and V. Heuring

29 Two bits:,,, Gray Code Three bits:,,,,,,, Successive bit patterns only differ at position For Karnaugh maps, adjacent s represent minterms that can be simplified using the rule: C + C = ( + )C = C = C C UMC, CMSC33, Richard Chang <chang@umbc.edu>

30 Karnaugh Maps Implicant: rectangle with, 2, 4, 8, 6... s Prime Implicant: an implicant that cannot be extended into a larger implicant Essential Prime Implicant: the only prime implicant that covers some K-map lgorithm (not from M&H):. Find LL the prime implicants. e sure to check every and to use don t cares. 2. Include all essential prime implicants. 3. Try all possibilities to find the minimum cover for the remaining s. UMC, CMSC33, Richard Chang <chang@umbc.edu>

31 K-map Example CD d CD d d d D d d D C C + C D + D UMC, CMSC33, Richard Chang <chang@umbc.edu>

32 Notes on K-maps lso works for POS Takes 2 n time for formulas with n variables Only optimizes two-level logic Reduces number of terms, then number of literals in each term ssumes inverters are free Does not consider minimizations across functions Circuit minimization is generally a hard problem Quine-McCluskey can be used with more variables CD tools are available if you are serious UMC, CMSC33, Richard Chang <chang@umbc.edu>

33 Next Time Continue Circuit Simplification Homework 4 due Homework 5 assigned UMC, CMSC33, Richard Chang <chang@umbc.edu>