Basic Gate Repertoire

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Maud Banks
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1 asic Gate Repertoire re we sure we have all the gates we need? Just how many two-input gates are there? ND OR NND NOR SURGE Hmmmm all of these have 2-inputs (no surprise) each with 4 combinations, giving 2 2 output cases = 2 4 = 6 How many ways are there of assigning 4 outputs? 6. Fall 25 Lecture 3, Slide

2 There are only so many gates There are only 6 possible 2-input gates some we know already, others are just silly I N P U T Z E R O N D > > X O R O R N O R X N O R N O T <= N O T <= N N D O N E How many of these gates can be implemented using a single MOS gate? MOS gates are inverting; we can always respond positively to positive transitions by cascaded gates. ut suppose our logic yielded cheap positive functions, while inverters were expensive 6. Fall 25 Lecture 3, Slide 2

3 Fortunately, we can get by with a few basic gates ND, OR, and NOT are sufficient (cf oolean Expressions): > XOR y y =+ That is just DeMorgan s Theorem! =+ + = How many different gates do we really need? 6. Fall 25 Lecture 3, Slide 3

4 One will do! NNDs and NORs are universal: = = = = = = h!, but what if we want more than 2 inputs? 6. Fall 25 Lecture 3, Slide 4

5 I think that I shall never see a circuit lovely as N 2 log 2 N N-input TREE has O( log N ) levels... Signal propagation takes O( log N ) gate delays. Question: an EVER N-Input oolean function be implemented as a tree of 2-input gates? 6. Fall 25 Lecture 3, Slide 5

6 Here s a Design pproach Truth Table -it s systematic! -it works! -it s easy! -are we done yet??? ) Write out our functional spec as a truth table 2) Write down a oolean expression for every in the output = ) Wire up the gates, call it a day, and declare success! This approach will always give us oolean expressions in a particular form: SUM-OF-PRODUTS 6. Fall 25 Lecture 3, Slide 6

7 Straightforward Synthesis We can implement SUM-OF-PRODUTS with just three levels of logic. INVERTERS/ND/OR Propagation delay -- No more than 3 gate delays (well, it s actually O(log N) gate delays) 6. Fall 25 Lecture 3, Slide 7

8 Logic Simplification an we implement the same function with fewer gates? efore trying we ll add a few more tricks in our bag. OOLEN LGER: OR rules: a + =, a + = a, a + a = a ND rules: a = a, ao =, aa = a ommutative: a + b = b + a, ab = ba ssociative: (a + b) + c = a + (b + c), (ab)c = a(bc) Distributive: a(b+c) = ab + ac, a + bc = (a+b)(a+c) omplements: bsorption: a + a =, a + ab = a, aa = a + ab = a + b Reduction: DeMorgan s Law: a ( a + b) = a, a( a + b) = ab ab + ab = b, ( a + b)( a + b) = a + b = ab, ab = a + b b 6. Fall 25 Lecture 3, Slide 8

9 oolean Minimization: n lgebraic pproach Lets (again!) simplify an t he come up with a new example??? = Using the identity α + α = α For any expression α and variable : = Hey, I could write program to do That! = + + = + 6. Fall 25 Lecture 3, Slide 9

10 Karnaugh Maps: Geometric pproach K-Map: a truth table arranged so that terms which differ by exactly one variable are adjacent to one another so we can see potential reductions easily. Truth Table Here s the layout of a 3-variable K-map filled in with the values from our truth table: \ Why did he shade that row Gray? It s cyclic. The left edge is adjacent to the right edge. (It s really just a flattened out cube). 6. Fall 25 Lecture 3, Slide

$On to Hyperspace 4-variable K-map for a multipurpose logic gate: = + if if if if D D D D = = = = \ D\ gain it s$

11 On to Hyperspace 4-variable K-map for a multipurpose logic gate: = + if if if if D D D D = = = = \ D\ gain it s cyclic. The left edge is adjacent to the right edge, and the top is adjacent to the bottom. 6. Fall 25 Lecture 3, Slide

12 Finding Subcubes We can identify clusters of irrelevent variables by circling adjacent subcubes of s. subcube is just a lower dimensional cube. \ \ D\ The best strategy is generally a greedy one. - ircle the largest N-dimensional subcube (2 N adjacent s) 4x4, 4x2, 4x, 2x2, 2x, x - ontinue circling the largest remaining subcubes (even if they overlap previous ones) - ircle smaller and smaller subcubes until no s are left. 6. Fall 25 Lecture 3, Slide 2

13 Write Down Equations Write down a product term for the portion of each cluster/subcube that is invariant. ou only need to include enough terms so that all the s are covered. Result: a minimal sum of products expression for the truth table. \ \ D\ = + = + D + D + D We re done! 6. Fall 25 Lecture 3, Slide 3

14 Recap: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes, selecting the largest available subcube at each step, even if it involves some overlap with previous cubes, until all ones are covered. (Try: 4x4, 2x4 and 4x2, x4 and 4x, 2x2, 2x and x2, finally x) 3) Write down the minimal SOP realization Truth Table JRGON: JRGON: The The circled circled terms terms are are called called implicants. implicants. n n implicant implicantnot not completely completely contained contained in in another another implicant implicantis is called called a a prime prime implicant. implicant. \ = + 6. Fall 25 Lecture 3, Slide 4

15 Practical SOP Implementation NND-NND =+ Pushing ubbles NOR-NOR =+ xyz = x + y + z ou might think all these extra inverters would make this structure less attractive. However, quite the opposite is true. x + y = 6. Fall 25 Lecture 3, Slide 5 xy

PLs have a programmable decoder (ND plane) with fixed selector logic (OR plane).

16 PLs: Programmable rray Logic User-programmable NDs Fixed ORs nother approach to structured logic design is Programmable rray Logic (PL). These were once popular off-the-shelf devices. They basically replaced TTL gates in the 8s and fueled the minicomputer revolution. PLs have a programmable decoder (ND plane) with fixed selector logic (OR plane). These devices were useful for implementing large fan-in gates and SOP logic expressions. They are purchased as unprogrammed chips and configured in the field using an inexpensive programmer. 6. Fall 25 Lecture 3, Slide 6

17 Logic that defies SOP simplification i S o o Full dder F i S / O / S S = o = an simplify the carry out easily enough, eg... o = + + ut, the sum, S, doesn t have a simple sum-of-products implementation even though it can be implemented using only two 2-input XOR gates. 6. Fall 25 Lecture 3, Slide 7

18 Logic Synthesis Using MUXes Truth Table If is then copy to, otherwise copy to 2-input Multiplexer 4-input Mux implemented as a tree I I S I 2 S I 3 S S S schematic Gate symbol 6. Fall 25 Lecture 3, Slide 8

19 Systematic Implementation of ombinational Logic onsider implementation of some arbitrary oolean function, F(,)... using a MULTIPLEXER as the only circuit element: in out,, in Full-dder arry Out Logic out 6. Fall 25 Lecture 3, Slide 9

20 Systematic Implementation of ombinational Logic Same function as on previous slide, but this time let s use a 4-input mux in out, Full-dder arry Out Logic 2 3 out 6. Fall 25 Lecture 3, Slide 2

21 General Table Lookup Synthesis Fn(,) MUX Logic Fn(,) Muxes Muxesare are UNIVERSL! UNIVERSL! S S = = Generalizing: In theory, we can build any -output combinational logic block with multiplexers. 2 N For an N-input function we need a input mux. IG Multiplexers? How about -input function? 2-input? In In future future technologies technologies muxes muxesmight might be be the the natural natural gate. gate. 6. Fall 25 Lecture 3, Slide 2 S S = What does that one do?

22 Mux s Guts decoder generates all possible product terms for a set of inputs Decoder Selector Multiplexers 2 3 I I I I can be constructed into two sections: DEODER that identifies the desired input,and a SELETOR that enables that input onto the output. Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs 6. Fall 25 Lecture 3, Slide 22

23 Using Memory as a Programmable Logic Device 2 M+N INPUTS bit lines word lines ol. ol. 2 ol. 3 N M Row ddress Decoder olumn Multiplexor ol. 2 M Row Row 2 Row 2 N memory cell (one bit) F(INPUTS) 6. Fall 25 Lecture 3, Slide 23

24 FPG Logic lock 6. Fall 25 Lecture 3, Slide 24

Logic Synthesis. Late Policies. Wire Gauge. Schematics & Wiring

Logic Synthesis. Late Policies. Wire Gauge. Schematics & Wiring Late Policies Logic Synthesis Primitive logic gates, universal gates Truth tables and sum-of-products Logic simplification Karnaugh Maps, Quine-Mcluskey General implementation techniques: muxes and look-up