CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps
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1 CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang <chang@umbc.edu>
2 Last Time & efore Returned midterm exam Half adders & full adders Ripple carry adders vs carry lookahead adders Propagation delay Multiplexers UMC, CMSC33, Richard Chang
3 Data Inputs -27 ppendix : Digital Logic Multiplexer D D D 2 D 3 F F D D D 2 D 3 Control Inputs F = D + D + D 2 + D 3 Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
4 -3 ppendix : Digital Logic Demultiplexer D F = D F = D F F F 2 F 3 F 2 = D F 3 = D D F F F 2 F 3 Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
5 -32 ppendix : Digital Logic Gate-Level Implementation of DEMUX F D F F 2 F 3 Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
6 -33 ppendix : Digital Logic Decoder Enable = Enable = D D Enable D 2 D 3 D D D 2 D 3 D D D 2 D 3 D = D = D 2 = D3 = Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
7 -34 ppendix : Digital Logic Gate-Level Implementation of Decoder D D D 2 D 3 Enable Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
8 -35 ppendix : Digital Logic Decoder Implementation of Majority Function Note that the enable input is not always present. We use it when discussing decoders for memory. C M Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
9 -36 Priority Encoder ppendix : Digital Logic n encoder translates a set of inputs into a binary encoding. Can be thought of as the converse of a decoder. priority encoder imposes an order on the inputs. i has a higher priority than i+ 2 3 F F 2 3 F F F = F = Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
10 -37 ppendix : Digital Logic ND-OR Implementation of Priority Encoder F 2 3 F Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
11 -38 C ppendix : Digital Logic Programmable Logic rray OR matrix PL is a customizable ND matrix followed by a customizable OR matrix. lack box view of PL: C PL F F Fuses ND matrix Principles of Computer rchitecture by M. Murdocca and V. Heuring F F 999 M. Murdocca and V. Heuring
12 -39 C ppendix : Digital Logic Simplified Representation of PL Implementation of Majority Function C C C C Principles of Computer rchitecture by M. Murdocca and V. Heuring F (Majority) F (Unused) 999 M. Murdocca and V. Heuring
13 -4 ppendix : Digital Logic Full dder i i C i S i C i+ i i C i+ Full adder S i C i Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
14 -43 C in ppendix : Digital Logic PL Realization of Full dder Sum C out Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
15 -3 ppendix : Reduction of Digital Logic Reduction (Simplification) of oolean Expressions It is usually possible to simplify the canonical SOP (or POS) forms. smaller oolean equation generally translates to a lower gate count in the target circuit. We cover three methods: algebraic reduction, Karnaugh map reduction, and tabular (Quine-McCluskey) reduction. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
16 -7 ppendix : Reduction of Digital Logic Karnaugh Maps: Venn Diagram Representation of Majority Function Each distinct region in the Universe represents a minterm. This diagram can be transformed into a Karnaugh Map. C C C C C C C C C Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
17 -8 ppendix : Reduction of Digital Logic K-Map for Majority Function Place a in each cell that corresponds to that minterm. Cells on the outer edge of the map wrap around Minterm Index C F C -side -side balance tips to the left or right depending on whether there are more s or s. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
18 -9 ppendix : Reduction of Digital Logic djacency Groupings for Majority Function C F = C + C + Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
19 - ppendix : Reduction of Digital Logic Minimized ND-OR Majority Circuit C F F = C + C + The K-map approach yields the same minimal two-level form as the algebraic approach. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
20 - ppendix : Reduction of Digital Logic K-Map Groupings Minimal grouping is on the left, non-minimal (but logically equivalent) grouping is on the right. To obtain minimal grouping, create smallest groups first. CD CD F = C + C D + C + C D F = D + C + C D + C + C D Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
21 Example Requiring More Rules CD D C UMC, CMSC33, Richard Chang <chang@umbc.edu>
22 -2 ppendix : Reduction of Digital Logic K-Map Corners are Logically djacent CD F = C D + D + Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
23 -3 ppendix : Reduction of Digital Logic K-Maps and Don t Cares There can be more than one minimal grouping, as a result of don t cares. CD d CD d d d F = C D + D F = D + D Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
24 Two bits:,,, Gray Code Three bits:,,,,,,, Successive bit patterns only differ at position For Karnaugh maps, adjacent s represent minterms that can be simplified using the rule: C + C = ( + )C = C = C C UMC, CMSC33, Richard Chang <chang@umbc.edu>
25 Karnaugh Maps Implicant: rectangle with, 2, 4, 8, 6... s Prime Implicant: an implicant that cannot be extended into a larger implicant Essential Prime Implicant: the only prime implicant that covers some K-map lgorithm (not from M&H):. Find LL the prime implicants. e sure to check every and to use don t cares. 2. Include all essential prime implicants. 3. Try all possibilities to find the minimum cover for the remaining s. UMC, CMSC33, Richard Chang <chang@umbc.edu>
26 K-map Example CD d CD d d d D d d D C C + C D + D UMC, CMSC33, Richard Chang <chang@umbc.edu>
27 Notes on K-maps lso works for POS Takes 2 n time for formulas with n variables Only optimizes two-level logic Reduces number of terms, then number of literals in each term ssumes inverters are free Does not consider minimizations across functions Circuit minimization is generally a hard problem Quine-McCluskey can be used with more variables CD tools are available if you are serious UMC, CMSC33, Richard Chang <chang@umbc.edu>
28 Circuit Minimization is Hard Unix systems store passwords in encrypted form. User types in x, system computes f(x) and looks for f(x) in a file. Suppose we us 64-bit passwords and I want to find the password x, such that f(x) = y. Let gi(x) = if f(x) = y and the ith bit of x is otherwise. If the ith bit of x is, then gi(x) outputs for every x and has a very, very simple circuit. If you can simplify every circuit quickly, then you can crack passwords quickly. UMC, CMSC33, Richard Chang <chang@umbc.edu>
29 -6 ppendix : Reduction of Digital Logic 3-Level Majority Circuit K-Map Reduction results in a reduced two-level circuit (that is, ND followed by OR. Inverters are not included in the two-level count). lgebraic reduction can result in multi-level circuits with even fewer logic gates and fewer inputs to the logic gates. C M Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
30 CD CD CD D D D C C C CD CD CD D D D C C C
CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification
CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization
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CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
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