UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY
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1 UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY
2 Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational circuit consists of logic gates whose outputs at any time are determined by the current input values. It has no memory elements No feedback from output to input
3 ombinational ircuits Output is function of input only i.e. no feedback n inputs ombinational ircuits m outputs When input changes, output may change (after a delay)
4 ombinational ircuits nalysis Given a circuit, find out its function F? Function may be epressed as: F2? oolean function Truth table Design Given a desired function, determine its circuit Function may be epressed as: oolean function? Truth table
5 nalysis Procedure oolean Epression pproach T 2 = T =++ F 2 =( + )( + )( + ) F T 3 =''+''+'' F 2 =++ F 2 F =''+''+''+ F 2 =++
6 nalysis Procedure Truth Table pproach F F 2 = = = = = = = = F = = F 2 = =
7 nalysis Procedure Truth Table pproach = = = F F F 2 = = = = = = = F 2 = =
8 nalysis Procedure Truth Table pproach = = = = = = = = F F F 2 = = F 2 = =
9 nalysis Procedure Truth Table pproach = = = = = = = = F F F 2 = = F 2 = =
10 nalysis Procedure Truth Table pproach = = = = = = = = F F F 2 = = F 2 = =
11 nalysis Procedure Truth Table pproach = = = = = = = = F F F 2 = = F 2 = =
12 nalysis Procedure Truth Table pproach = = = = = = = = = = F F 2 F F 2 = =
13 nalysis Procedure Truth Table pproach = = = = = = = = = = = = F =''+''+''+ F F 2 F F 2 F 2 =++
14 Design Procedure Given a problem statement: Determine the number of inputs and outputs Derive the truth table Simplify the oolean epression for each output Produce the required circuit Eample: Design a circuit to convert a D code to Ecess 3 code 4-bits -9 values? 4-bits Value+3 Eastern Mediterranean University 3 / 65
15 Design Procedure D-to-Ecess 3 onverter D w y z D w = ++D D y = D +D z = D D D = + D+ D
16 Design Procedure D-to-Ecess 3 onverter D w y z D w = + (+D) = (+D) + (+D) y = (+D) + D z = D w y z
17 inary dder Half dder dds -bit plus -bit y H S Produces Sum and arry y S y + y S S
18 inary dder Full dder dds -bit plus -bit plus -bit Produces Sum and arry y z S y yz F + y + z S z S = y'z'+'yz'+'y'z+yz = y z y z = y + z + yz S
19 inary dder Full dder y z y z S = y'z'+'yz'+'y'z+yz = y z = y + z + yz y z y z y z y z S y z y z y z y z S y z
20 inary dder Full dder y H H S z y S z
21 inary dder y 3 2 y 3 y 2 y y inary dder arry Propagate ddition c 3 c 2 c y 3 y 2 y y y S 3 S 2 S S S 3 S 2 S S 3 2 y 3 y 2 y y F F F F 4 S 3 3 S 2 2 S S
22 inary dder arry Propagate dder y 7 y 6 y 5 y y 3 y 2 y y y P y P S 3 S 2 S S S 3 S 2 S S S 7 S 6 S 5 S 4 S 3 S 2 S S
23 inary dder arry Propagation arry propagation When the correct outputs are available The critical path counts (the worst case) (,, ) ( 5, S 4 ) When 4-bits full-adder 8 gate levels (n-bits: 2n gate levels) Full dder with P and G
24 Parallel dders Reduce the carry propagation delay Employ faster gates Look-ahead carry (more comple mechanism, yet faster) arry propagate: P i = i i arry generate: G i = i i Sum: S i = P i i arry: i+ = G i +P i i = Input carry = G +P 2 = G +P = G +P (G +P ) = G +P G +P P 3 = G 2 +P 2 2 = G 2 +P 2 G +P 2 P G + P 2 P P
25 inary Subtractor Use 2 s complement with binary adder y = + (-y) = + y y 3 y 2 y y y inary dder i S 3 S 2 S S F 3 F 2 F F
26 inary dder/subtractor M: ontrol Signal (Mode) M= F = + y M= F = y 3 2 y 3 y 2 y y M y inary dder i S 3 S 2 S S F 3 F 2 F F
27 Logic diagram arry Look-ahead dder (/2) Logic Diagram of arry Look-ahead Generator
28 arry Look-ahead dder (2/2) 4-bit carry-look ahead adder Propagation delay of 3, 2 and are equal. 4-it dder with arry Look-ahead
29 Decimal dder decimal adder requires a minimum of 9 inputs and 5 outputs digit requires 4-bit Input: 2 digits + -bit carry Output: digit + -bit carry D adder Perform the addition of two decimal digits in D, together with an input carry from a previous stage. The output sum cannot be greater than 9 (9+9+)
30 D dder 4-bits plus 4-bits Operands and Result: to y 3 y 2 y y y S 3 S 2 S S X +Y 3 2 y 3 y 2 y y Sum y S 3 S 2 S S + = + = + 2 = = 9 + = + = = = 2 + = = 2 Invalid ode Wrong D Value
31 D dder X +Y 3 2 y 3 y 2 y y Sum y S 3 S 2 S S Required D Output Value 9 + = 9 = = = = = = 2 = = 3 = = 4 = = 5 = = 6 = = 7 = = 8 =
32 D dder orrect inary dder s Output (+6) If the result is between and F If y = S 3 S 2 S S Err S S 3 S S 2 Err = S 3 S 2 + S 3 S
33 D dder 3 2 y 3 y 2 y y y inary dder i S 3 S 2 S S Err y inary dder i S 3 S 2 S S y S 3 S 2 S S
34 Overflow Unsigned inary Numbers 3 2 y 3 y 2 y y arry F 2 s omplement Numbers F F 4 S 3 3 S 2 2 S S 3 2 F y 3 y 2 y y F F F F Overflow 4 S 3 3 S 2 2 S S
35 inary Multiplier
36 4-it y 3-it inary Multiplier
37 Decoders Etract Information from the code inary Decoder Eample: 2-bit inary Number Only one lamp will turn on inary Decoder
38 inary Decoder Decoders 2-to-4 Line Decoder Y 3 I I y 3 y 2 y y Y 2 Y Y I I Y 3 Y 2 Y Y I I Y3 I I Y2 I I Y I I Y I I
39 inary Decoder Decoders 3-to-8 Line Decoder Y 7 Y 6 I I 2 I I 2 I I I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y 5 Y 4 Y 3 Y 2 Y Y I I I I I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I I 2 I I
40 inary Decoder Decoders Enable ontrol Y 3 I I E Y 3 Y 2 Y Y Y 2 Y Y E I I Y 3 Y 2 Y Y I I E
41 Decoders inary Decoder inary Decoder Epansion I 2 I I I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y I I E I I E Y 3 Y 2 Y Y Y 3 Y 2 Y Y Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y
42 inary Decoder Decoders inary Decoder ctive-high / ctive-low I I Y 3 Y 2 Y Y I I Y 3 Y 2 Y Y Y 3 Y 2 I I Y 3 Y 2 Y I Y 3 Y 2 Y Y I I Y I Y Y
43 Implementation Using Decoders Each output is a minterm ll minterms are produced Sum the required minterms Eample: Full dder S(, y, z) = (, 2, 4, 7) (, y, z) = (3, 5, 6, 7) y z inary Decoder I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y S
44 Implementation Using Decoders inary Decoder inary Decoder y z I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y y z I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y S S
45 Seven-Segment Decoder w y z a b c d e f g w y z? D code y w z a b c d a = w + y + z + z b =... c =... d =... e f g e f d a g b c
46 Encoders Put Information into code inary Encoder Eample: 4-to-2 inary Encoder Only one switch should be activated at a time 2 3 inary Encoder y y 3 2 y y
47 Encoders inary Encoder Octal-to-inary Encoder (8-to-3) I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y Y Y Y 2 I I I I I I I I I I I I 4 2 I 7 I 6 I 5 I 4 I 3 I 2 I I I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y Y 2 Y Y
48 Priority Encoders Priority Encoder 4-Input Priority Encoder I 3 I 2 I I Y Y V I 3 I 2 I 3 I 2 I I V Y Y Y Y I I 3 I I 2 Y Y V I I I I I I I I I I I Y V
49 Encoder / Decoder Pairs inary Encoder inary Decoder I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y
50 Digital Multipleer S S Y I I I I I 2 MUX I 3 S S Y I 2 I 3
51 Multipleers 2-to- MUX I I I MUX S Y I Y S 4-to- MUX I I I I I 2 MUX I 3 S S Y I 2 I 3 Y S S
52 Multipleers Quad 2-to- MUX 3 y 3 I I MUX Y S 3 2 Y 3 Y 2 Y Y 2 y 2 y y I I I I I I MUX Y S MUX Y S MUX Y S 3 2 S E MUX S E Y 3 Y 2 Y Y S
53 Multipleers Quad 2-to- MUX Y 3 Y 2 Y Y MUX S E Y 3 Y 2 Y Y Etra uffers S E
54 Implementation Using Multipleers Eample F(, y) = (,, 3) y F I I I 2 MUX I 3 S S y Y F
55 Implementation Using Using Multipleers Eample F(, y, z) = (, 2, 6, 7) y z F I I I 2 I 3 I MUX 4 I 5 I 6 I 7 S2 S S y z Y F
56 Implementation Using Using Multipleers Eample F(, y, z) = (, 2, 6, 7) y z F F = z F = z F = F = z z I I I 2 MUX I 3 S S y Y F
57 Implementation Using Using Multipleers Eample F(,,, D) = (, 3, 4,, 2, 3, 4, 5) D F F = D F = D F = D F = F = F = D F = F = D D D D I I I 2 I 3 I MUX 4 I 5 I 6 I 7 S2 S S Y F
58 Multipleer Epansion 8-to- MUX using Dual 4-to- MUX I I I 2 I 3 I I I 2 MUX I 3 S S Y I 4 I 5 I 6 I 7 I I I 2 MUX I 3 S S Y I I MUX S Y Y S 2 S S
59 DeMultipleers I DeMUX S S Y 3 Y 2 Y Y Y 3 I S S Y 2 Y Y S S Y 3 Y 2 Y Y I I I I
60 Multipleer / DeMultipleers Pairs MUX DeMUX I 7 I 6 I 5 I 4 I 3 I 2 I I Y I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y S 2 S S S 2 S S Synchronize 2 y 2 y y
61 DeMultipleers / Decoders inary Decoder I DeMUX S S Y 3 Y 2 Y Y I I E Y 3 Y 2 Y Y S S Y 3 Y 2 Y Y I I I I E I I Y 3 Y 2 Y Y
62 Magnitude omparator ompare 4-bit number to 4-bit number 3 Outputs: <, =, > Epandable to more number of bits Magnitude omparator < = > ) ( ) ( ) (
63 Magnitude omparator (<) (>) (=)
64 Magnitude omparator y 7 y 6 y 5 y y 3 y 2 y y I (>) I (=) I (<) Magnitude omparator < = > I (>) I (=) I (<) Magnitude omparator < = > < = >
65 Thank you
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