Binary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 P Q

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1 Digital Arithmetic In Chapter 2, we have discussed number systems such as binary, hexadecimal, decimal, and octal. We have also discussed sign representation techniques, for example, sign-bit representation and 2 s complement representation. Our discussions were extended to CD and other codes, and simple arithmetic operations such as addition and subtraction using binary numbers. In this chapter, we will discuss the related digital circuits capable of performing elementary arithmetic operations, which are essential for computers and some other digital systems. After the completion of this chapter, the reader would be able to understand and design different types of adder and subtractor circuits, realize the importance of carry propagation, distinguish between binary addition and CD addition, design 1 s and 2 s complement-based digital circuits, be familiar with the arithmetic logic unit (ALU), and design digital comparators with cascading inputs.

2 194 Digital Electronics 6.1 inary Addition Addition is the most elementary arithmetic operation. Therefore, single-bit binary addition may be taken as the basic building block of digital arithmetic. Let P and Q be the two binary variables (each of 1-bit). Their sum may be any one of the following four, depending upon the magnitudes of P and Q: inary variable P inary variable Q Sum (P + Q) = 0 = 1 = 1 = 10 Carry Note that only in the last case, when both operators are 1, a carry is generated and the sum becomes 0. If we consider only the primary bit of the result (Y), then the variations will be as presented in Table 6.1. Table 6.1 inary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 The reader might have already correlated Table 6.1 with the truth table of an XOR gate. As a matter of fact, we may refer to Figure 3.14(c) of Chapter 3 (truth table for XOR gate) to compare with Table 6.1. They are similar in nature, and therefore, if we use an XOR gate, as in Figure 6.1, it may also be referred to as the basic building block of 1-bit binary addition. However, the circuit is not capable of generating any carry bit when both operators are 1 (refer to the last row of Table 6.1). This problem is eliminated in the half-adder circuit, discussed in following section. P Q 2-input XOR gate Y XOR truth table Input Output P Q Y= P Q (a) (b) Figure 6.1 XOR gate as 1-bit basic adder (without carry bit) Half Adder Referring to Table 6.1, we may note that the carry bit is generated only when both P and Q are 1. For all other conditions of P and Q, the carry bit remains 0. The simplest solution, therefore, is to incorporate a 2-input AND gate in the circuit with P and Q as the two inputs, and the carry bit as the output (Figure 6.2). Observe that now the circuit is perfectly capable of functioning as presented in Table 6.1.

3 Digital Arithmetic 195 Y Carry out P Q Figure 6.2 Half-adder circuit (1-bit adder with carry-out) Time to Take a Test Draw the K-map for carry-out for the half adder Full Adder The reader might wonder that if the above circuit (Figure 6.2) is capable of performing addition, then why designate it as half adder? As a matter of fact, this circuit is yet unable to perform the addition operation in the case of multi-bit operators. We have already indicated that the decimal numbers are represented by a group of multi-bit binary numbers. If we add decimal 7 to decimal 3, when both are expressed in binary, then the situation demands multi-bit binary addition, which will be as follows: Carry bit decimal decimal 3 = decimal 10 We can observe here that after addition of two rightmost bits (1 and 1), the result is 0 and a carry bit of 1 is generated. This carry bit is shifted to the adjacent bit (at left) where we have to add not two bits but three bits including the carry bit. In the half-adder circuit described above (Figure 6.2), there is no provision of accommodating this third bit or carry bit. We need some additional circuit for that purpose. Note that the circuit of Figure 6.2 is capable of performing only the first addition, that is, the addition of the rightmost two bits where there is no third bit (carry bit) present. Reader, Remember! Carry generated due to the addition of several bits is known as carry-out. This carry-out becomes carry-in for the next bit at immediate left and must be considered for the next bit addition. Answer to TTTT: Q Q C P 0 0 out = P 0 1 P Q

4 196 Digital Electronics? Confusion Clearing Corner The full adder accepts carry-in as the third input, but the half adder does not have any provision for it. This is the basic difference between the half adder and the full adder. How do we design the circuit of a full adder? Let us start with its truth table. With two oolean operators P and Q, and a Carry in bit as input, we construct the truth table of a full adder with two outputs, namely Y (the sum or the main output) and Carry out, as presented in Table 6.2. Table 6.2 Truth table for full adder Input Output Carry in P Q Y Carry out Reader, Remember! We are considering Q as the least significant bit (LS). This will play an important role when we will consider the carry-propagation. The reader might have observed that there are two outputs (Y and Carry out ) against three inputs (Carry in, P, and Q). The main output Y will be 1, if there is an odd number of 1s within the three inputs. For an even number of 1s, the Y output will be 0. The Carry out output will be 1 if two or all the three inputs are 1. If only one input is 1 or if all the inputs are 0, then the Carry out will be 0. To generate the main output Y, we may use two XOR gates, one following the other, as shown in Figure 6.3. Through this XOR gate pair, first we are adding P and Q, and their sum is then added to the Carry in bit to generate the final sum Y. To generate the Carry out, we may use three 2-input AND gates, and their output may be fed to a 3-input OR gate as illustrated in Figure 6.3. This circuit may also be designed using a K-map, as discussed below. From the truth table of a full adder (Table 6.2), a K-map may be generated as shown in Figure 6.4 to obtain the expressions for Y and Carry out. Note that we may consider three separate loops to generate the expression for Carry out as Carry out = ( Carry in PQ + Carry in PQ) + (Carry in PQ + Carry in PQ ) + (Carry in P Q + Carry in PQ) which, after simplification, leads to the resultant expression as shown in Figure 6.4(b).

5 Digital Arithmetic 197 Y Carry out Carry in P Q Figure 6.3 Full adder circuit PQ PQ PQ PQ PQ PQ PQ PQ Carry in Carry in Carry in Carry in K-map for Y K-map for Carry out Y = Carry PQ + Carry PQ + Carry PQ + Carry PQ in in in in = Carry ( PQ + PQ) + Carry ( PQ + PQ) in = Carry ( P Q)+ Carry ( P Q) in in = Carry P Q in (a) Figure 6.4 in Carryout = PQ + Carryin P + Carryin Q (b) K-map for (a) sum Y and (b) Carry out for full adder The circuit shown in Figure 6.3 is known as 1-bit full adder and is generally represented by the symbol as illustrated in Figure 6.5(a). The timing diagram of this 1-bit full adder is presented in Figure 6.5(b). The reader may compare the timing diagram with the truth table of the full adder (Table 6.2). P Q Carry in 1-bit Full adder Y Carry out Q P Carry in Y Carry out (a) (b) Figure bit full adder: (a) symbol and (b) timing diagram

6 198 Digital Electronics As mentioned earlier, the circuit presented in Figure 6.3 is not the only circuit for performing the operation of a full adder; several other designs are also possible to achieve the same function in different ways. Time to Take a Test Redesign the full-adder circuit using two half adders and logic gates n-bit Parallel inary Adder As already indicated in the previous section, a binary addition is generally carried out for multiple binary digits for which several full adders are cascaded. Depending upon the system requirement, the number of full adders varies. However, in general, they are a multiple of 4. Figure 6.6 illustrates the schematic of a 4-bit binary adder consisting of four full adders with necessary interconnections. C out Y 3 Y 2 Y 1 C out C out C out Y 0 FA 3 FA 2 F FA 0 3 C in 2 C in 1 C in A 0 0 C in A 3 A 2 Figure 6.6 Schematic of a 4-bit binary adder In this case we are assuming that two 4-bit operands, namely A 0 A 3 and 0 3, are to be added by the 4-bit adder circuit, producing the 4-bit sum Y 0 Y 3 along with a carry-out bit (C out ). Therefore, four numbers of full adders, namely FA 0 FA 3, are provided in the circuit. Note that as there will not be any carry-in input for the least significant bit, the C in input of FA 0 is grounded to turn this input permanently 0. However, if used in cascade for multi-bit operations, the concerned C in input has to be interfaced with the previous C out output. The carry-out (C out ) generated by the first full adder (FA 0) becomes the carry-in (C in ) for the next higher bit adder (F). The carry-out from F is fed into the carry-in of FA 2 and so on. The final carry-out, after Answer to TTTT: Full-adder using two half adders and one OR gate. C in A Y C out

7 Digital Arithmetic 199 completion of 4-bit addition, is available from the C out of FA 3, that is, the leftmost full adder. The reader may note that MSI circuits are commercially available for multi-bit binary addition (see Table 6.4). The external signals of an integrated circuit (IC) capable of performing 4-bit binary addition will be as shown in Figure 6.7. If the IC has to perform an addition of the least significant four bits where no carry-in is applicable, the C in input of the device is grounded for 0 input. In other cases, the C in input is obtained from the previous C out. C out Y 3 Y 2 Y 1 Y 0 4-bit binary adder C in A 3 A 2 A 0 Figure 6.7 External signals of a 4-bit binary adder At this stage, the reader may be shared with a fact that apart from the purpose of simple 4-bit binary addition, the circuit illustrated in Figure 6.7 is incorporated in various other operations and, therefore, may be designated as one of the most widely used building blocks in digital circuits. Later in this chapter, we will discuss about a few more applications of this 4-bit binary adder Carry Look Ahead Adder In Section , we have introduced the term propagation delay, related to electronic circuits. We may recall that this propagation delay may be attributed to the activation and deactivation of diodes and transistors within any electronic circuit, which demands very small but a finite amount of time, say a few nanoseconds. The multi-bit adder circuit that we have discussed above is also affected by the propagation delay. This means that the generation of any one of its carry-out signal needs a few nanoseconds after receiving the corresponding stable input. Therefore, for any multi-bit adder circuit, this propagation delay will be cumulative as every carry-in is the outcome of the previous carry-out, because the carry propagates from one side to another like a ripple. This might create some amount of unwanted delays to generate the accurate final output after a valid initial input. For the purpose of visualization, we may consider a 64-bit adder composed of 16 numbers of 4-bit binary adders the same module as depicted in Figure 6.7. If we assume that the generation of each carry-out after a valid carry-in input takes 3 ns, then for 4-bit addition, it will demand 12 ns. Therefore, for 64-bit addition we will receive the final carry-out after = 192 ns. The same logic is equally valid even for the sum output, as the sum is also dependent on the carry-out of the previous bit.

8 200 Digital Electronics? Confusion Clearing Corner This carry propagation is very much similar to the collapsing of a card-house where one card falls over the next one, propagating the card-collapsing from one side to another. To overcome this problem, an additional circuit is incorporated within the adder circuit which looks ahead (backwards) and decides for any eventual carry directly. This is known as the carry look ahead adder. To understand the concept behind this design, we have to clearly visualize the conditions of carry-generation and carry-propagation Carry Generation Carry is generated only if both the input bits are 1, that is, if A and are the two input bits, then to generate any carry, both of these bits must be 1. Otherwise carry will not be generated. The reader may think that even if the value of one of these two bits A or is 0, a carry may still be generated if the carry-in bit is 1. The reader may note that such a case is called carry-propagation (not carry-generation) and we will discuss it during carry-propagation. Please note that generation and propagation are two different activities. If we designate G as the carry-generation function, then we may express our observation as G = A (6.1) If we consider the present bit as the nth bit, then we may rewrite the above function as G n = A n n (6.2) Carry Propagation A carry is propagated if any one of the two input bits A or is 1. If both A and are 0, a carry will never be propagated. On the other hand, if both A and are 1, then it will not propagate the carry but will generate the carry, as already described above. If we designate P as the carry-propagation function, then we may express it as P n = A n n (6.3) To further clarify the concept, let us go through the truth table of the full adder that we have already observed in Table 6.2, which is reproduced here as Table 6.3. Here, within the column of Carry out, the symbols differentiate carry-generation and carry-propagation. From the above discussions, it should be clear that the generation or propagation of a carry depends primarily on the A and inputs of the currently concerned bit and does not primarily depend on the status or condition of the previous bits or Carry in bit. Reader, Remember! Even if carry-in is 1, no carry will be generated if both A and are 0. This is the reason for considering A and as the primary contributors of the carry-propagation function.

9 Digital Arithmetic 201 Table 6.3 Carry-generation and carry-propagation Input Output Carry in P Q Y Carry out Legend: indicates carry generated indicates carry propagated? Confusion Clearing Corner The reader may note that (see Table 6.3) C out must be 1 if the carry is generated or propagated. If C out is 0, then the carry is neither generated nor propagated. Secondly, if both A and are 1, then it is a case of carry-generation. If it is not a case of carry-generation, then if C out is 1 and C in is also 1, then it is a case of carry-propagation Look Ahead Expressions Now, if we consider the nth bit of a multi-bit adder, then the sum (S) and the carry-out (C) for that nth bit may be expressed in terms of the carry-generation function (G) and the carry-propagation function (P) as S n = P n + C n 1 C n = G n + P n C n 1 However, we already know that for any full adder, the sum and the carry for any bit (say n) may be expressed as (see Figure 6.4) S n = A n n C n 1 (6.6) C n = A n n + C n 1 (A n + n ) (6.7) Considering Eqs. (6.4) and (6.6), we may express P n as P n = A n n (6.8) Considering Eqs. (6.5) and (6.7), we may express G n as G n = A n n (6.9) Therefore, using Eq. (6.5), we may express the carry output for the first bit (bit 0 or n = 0) as C 0 = G 0 + P 0 C 1 (6.10) where G 0 = A 0 0 (6.11) (6.4) (6.5)

10 202 Digital Electronics and P 0 = A 0 0 (6.11a) Therefore, after replacing the values of G 0 and P 0 in Eq. (6.10), we obtain C 0 = A C 1 (A 0 0 ) (6.12) Similarly, from Eq. (6.5), we may express the carry output for the second bit (bit 1 or n = 1) as C 1 = G 1 + P 1 C 0 (6.13) y replacing the value of C 0 using Eq. (6.10), we may rewrite this as C 1 = G 1 + P 1 (G 0 + P 0 C 1 ) (6.14) which may be expanded as C 1 = 1 + ( 1 )(A (A 0 0 ) C 1 ) (6.15) Proceeding in the same way, we may develop the expressions for C 2 and C 3. Then we may construct the circuit for a 4-bit carry look ahead. However, for easier understanding, let us construct the circuit of a 2-bit carry look ahead. Note that after we complete the design of the 2-bit carry look ahead, we will use it to construct the circuit of a 2-bit carry look ahead adder bit Look Ahead Circuit To construct the circuit for a 2-bit carry look ahead, we will use Eqs. (6.10) and (6.14). We will consider P 0, G 0, P 1, G 1, and C 1 as the inputs. The outputs will be C 0 and C 1. The circuit is illustrated in Figure 6.8. The reader may note that the upper part of the circuit (output = C 0 ) is constructed following Eq. (6.10), while the lower part (output = C 1 ) is constructed using Eq. (6.14). With this 2-bit look ahead circuit, we are now in a position to construct the circuit of a 2-bit carry look ahead adder. C -1 P 0 G 0 C 0 P 1 C 1 G 1 Figure bit carry look ahead circuit Reader, Remember! From Figure 6.8, it may be observed that both C 0 and C 1 will be available at the same time (constant delay) as both are generated by 2-stage gates. Even for a 4-bit look ahead circuit, the delay will remain the same as the delay is not dependent upon the number of bits.

11 Digital Arithmetic bit Carry Look Ahead Adder Circuit In this 2-bit case, we have taken A 0, 0,, 1, and C 1 as the inputs as illustrated in Figure 6.9. The reader may wonder that if we are concerned with the bit-0 (LS) of the input, then why is C 1 considered. As a matter of fact, it should not be considered in the case of the addition of LS. However, these look ahead adders are used in cascade to take care of the multi-bit addition, and in such cases, C 1 will be necessary. In case of addition of LS, C 1 may be connected with GND to make it 0. C -1 A 0 P 0 C -1 0 C -1 S 0 1 G 0 P 1 2-bit carry look ahead C 0 P 0 S 1 P 1 G 1 C 1 Figure 6.9 A 2-bit carry look ahead adder The 2-bit carry look ahead circuit shown in Figure 6.8 forms the heart of the 2-bit carry look ahead adder circuit and is represented by a rectangular box in Figure 6.9. Note that the final output of this circuit will be S 0, S 1, and C 1. The concept explained for a 2-bit circuit may be extended to a 4-bit circuit. Time to Take a Test If A = 1, = 1, and C in = 1, then is it a case of carry-generation or carry-propagation or both? C Integrated Circuit Parallel Adder Integrated circuits are commercially available to perform binary addition. A few of these ICs are presented through Table 6.4. Note that the 4-bit look ahead carry generator is available as a separate package. All of these ICs are designed for cascading to cater for multi-bit operations. Out of the ICs of Table 6.4, we will refer 7483 and use it in different application circuits. Therefore, we briefly introduce 7483 at this place. The external pin diagram along with the signal nomenclature of IC 7483 is shown in Figure Observe that although functionally 7483 and are identical, their pin configurations are different. In the case of 74283, pin 8 will be GND and pin 16 will be V cc. IC 7483 allows two 4-bit binary operands A 4 and 1 4 along with a carry input designated as C 0. The carry-out is C 4, and S 1 S 4 will contain the 4-bit sum of the input. As already indicated, the device contains a carry look ahead circuit and is capable of performing the 4-bit addition within an average time of 15 ns. Answer to TTTT: This is a case of carry-generation as both A and are 1. In this case, C in does not matter.

12 204 Digital Electronics Table 6.4 Adder ICs Part number Description Number of IC pins Type Comments SN bit gated full adder 14 LSI Suitable for cascading SN bit binary full adder 14 MSI Suitable for cascading SN bit binary full adder 16 MSI With in-built carry look ahead SN74182 Look ahead carry generator 16 MSI 4-bit SN bit binary full adder with fast carry 16 MSI Pin configuration is different from 7483 A S S 4 A C C 0 V cc 5 12 GND S A S 1 Figure 6.10 Pin diagram of 7483 (4-bit binary full adder) 6.2 CD Addition In Chapter 2 (see Section 2.5), we have introduced the CD numbers where each decimal digit is expressed through a 4-bit binary equivalent. The reader may refer to Table 2.2 for the conversion of CD into other number systems. Although CD counters and CD to 7-segment decoder cum drivers (7447) are more common in application areas, the CD addition through a dedicated electronic circuit is not so common in industry. However, it will be interesting for the reader to be acquainted with the special circuit features necessary for the CD addition. The CD addition is performed with CD numbers as inputs. The output of the addition will also be in CD. The addition operation is performed in group of 4 bits of binary numbers representing one CD digit. The general rule followed in this addition is, if the result exceeds 9, then add 6. We explain this through an appropriate example. Let us assume that we will add decimal 8 to decimal 4, and we know that the result will be decimal 12. Note that although the inputs are of one decimal digit, the result is of two decimal digits. Now, the CD equivalent for decimal 8 will be 1000 and CD for decimal 4 will be Adding both will produce 1100 in binary. Observe that the decimal equivalent of binary 1100 is 12. However, the CD equivalent of decimal 12 will be 8-bit wide (4-bit/CD digit 2 CD digits) Remember that in CD, it becomes

13 Digital Arithmetic bit binary as each CD digit is converted into 4-bit binary. To convert the binary result 1100 into its CD equivalent , or for any binary to CD conversion after a CD addition, we adopt the following procedures: Step 1: Check if the result of the addition is more than 9. If not, no action required. Step 2: If yes, then add 6 to the result. Step 3: Consider the carry obtained after the addition of 6 for the next CD digit. Going back to our example, as the result of our CD addition of 1000 and 0100 is 1100, which is more than 9, we add 6 (or 0110 in binary) to the result. The result is now changed to in 5-bit format or in 8-bit format, whose corresponding CD value is CD Adder The maximum value of both CD operators in the case of CD addition will be 9 in decimal. Therefore, the range of the sum will vary from 0 (if both CD operators are 0) to 18 in decimal (if both CD operators are 9 in decimal). The binary representation of all the possible outputs of the single-digit CD addition is presented in Table 6.5. Table 6.5 inary range of 1-digit CD addition S 3 S 2 S 1 S 0 C out X (indicates sum more than 9) Sum in decimal In this table we have incorporated a variable X, which is 1 if the result of the addition is more than 9; otherwise, the value of X is 0. We may now formulate the relation to generate X from S 0, S 1, S 2, S 3, and C out. We may observe from Table 6.5 that

14 206 Digital Electronics (i) X must be 1 if C out is 1. (This incorporates decimal range from 16 to 18). (ii) X must be 1 if both S 2 and S 3 are 1s (takes care of range from 12 to 15). (iii) X must be 1 if both S 1 and S 3 are 1s (covers the range from 10 to 11). (iv) In all the remaining cases, X must be 0 (remaining range from 0 to 9). It is now possible for us to construct a circuit incorporating these features. We may use any 4-bit full adder available to us (say 7483). The input for the first adder will be two CD digits with any eventual carry from the previous CD digit addition. The main output from this adder, namely S 0 S 3, may be directly fed to one of the 4-bit inputs of the second adder, say, into A 0 A 3. The carry-in input of this second adder is to be permanently grounded along with the 0 and 3 input pins. To verify whether the result of the CD addition is greater than 9 or not, and if eventually it is more than 9, then to add 6 to the result, we will use two 2-input AND gates and one 3-input OR gate as shown in Figure Note that the input of the first AND gate is obtained from S 1 and S 3 outputs of the first adder. The input for the second AND gate is obtained from S 2 and S 3 outputs of the first adder. The output from both of these AND gates along with the carry-out output of the first adder are fed to the 3-input OR gate. The output from this 3-input OR gate is directly connected with the 1 and 2 inputs of the second adder. The reader is encouraged to verify that the following circuit checks the condition and, if necessary, adds 6 to the result. Otherwise, the circuit will add zero and allow the output from the first adder to pass undistorted through the second adder. CD output with carry S 0 A 0 S 1 S 2 S 3 4-bit inary Full Adder A 2 A 3 3 C out C in S 0 S 1 S 2 S 3 4-bit inary Full Adder C out A 0 A 2 A C in Two CD digits' input with carry Figure 6.11 CD adder with carry using 7483

15 Digital Arithmetic 207 To conclude our discussions on CD addition, the reader may be reminded that as a normal practice, CD addition is performed with multiple CD digits, and the CD adder we have designed will be necessary in multiple numbers depending upon the number of CD digits for the CD operators. Time to Take a Test Perform CD addition of 64 and inary Subtraction Algebraically, the process of subtraction is similar to the process of addition, with only one difference. In the case of subtraction, the sign plays a role. Take the case of the addition of positive integers. The result will always be positive and we need not worry about its sign. Now, take the case of the subtraction of positive integers. Depending upon the magnitude, the result might be either positive or negative. There are several methods to construct the circuit for performing subtraction. We may conduct it either by direct straightforward method, which we are about to discuss in this section, or we may adopt the 2 s complement scheme, which we will discuss in the next section. The reader may recall that we have already introduced the 2 s complement method of number representation in Chapter 2 (see Section 2.7.2) Half Subtractor If we consider P and Q to be two binary operators, each with only one binary digit, then the result of subtraction, P Q, may be any one of the following four, depending upon the magnitudes of P and Q: inary variable P inary variable Q Result (P Q) = 0 = 1 = 1 = 0 orrow = 1 The truth table for 1-bit subtraction with two operators P and Q as inputs and Y as the output is presented in Table 6.6. The reader may compare this table with Table 6.1 the table we have prepared for 1-bit binary addition. Note that the situation of Table 6.6 will be different if Y = Q P, whereas in the case of Table 6.1, it will remain the same if Y = Q + P. Therefore, in the case of subtraction, even if we consider it as algebraic addition, we must know which one of the two operators is having the negative sign; in our case, it is Q. The comparison between Tables 6.1 and 6.6 indicates that the Y output is identical in both cases. Therefore, we may form the expression Y = P Q (6.16) Answer to TTTT: 64 = and 46 = The CD addition of the two rightmost digits gives 1010 which is more than 9. Therefore, adding 0110 with it produces 0000 with a carry of 1. The addition of the next two CD digits along with the carry gives 1011, which is again more than 9. Therefore, adding 0110 gives 0001 with a carry 1. Therefore, the final result is in CD or 110 in decimal.

16 208 Digital Electronics However, for binary addition, the condition P = Q = 1 generated a carry. In the case of binary subtraction, P = 0 and Q = 1 produces a borrow. We may express it by C = P Q (6.17) Therefore, we may slightly modify the half-adder circuit we have designed and incorporate an inverter gate with P before ANDing it to generate the C output. The relevant half-subtractor circuit is shown in Figure Table 6.6 inary subtraction (1-bit) P Q Y = P Q Comments orrow = orrow = orrow = orrow = 0 Y Carry out (orrow) P Q Figure 6.12 Half-subtractor circuit (Y = P Q) Full Subtractor The limitation of the half-subtractor circuit discussed above is its inability to cater for multi-bit subtraction, where borrow from one bit propagates to the next bit, as there is no provision for borrow-in (in the halfsubtractor circuit). To eliminate this problem, we may design the full subtractor which will perform one-bit subtraction in multi-bit operations. The truth table for the full subtractor is presented in Table 6.7. The reader may note the differences between Tables 6.7 and 6.2. Table 6.7 Truth table for full subtractor Input Output Carry in P Q Y = P Q Carry in Carry out From this truth table, we can generate the K-map and then form the expressions for Y and Carry out, as shown in Figure If the reader is interested to compare these expressions with the expressions obtained for the full adder (see Figure 6.4), then it might be observed that the expressions for Y in both the cases are

17 Digital Arithmetic 209 identical. However, the expressions for carry-out differ for the P input. In the case of full adder, it was P; in the case of full subtractor, it is P. PQ PQ PQ PQ PQ PQ PQ PQ Carry in Carry in Carry in Carry in K-map for Y Y = Carry PQ + Carry PQ+ Carry PQ + Carry PQ in in in in = Carry ( PQ + PQ) + Carry ( PQ + PQ) in = Carry ( P Q)+ Carry ( P Q) in = Carryin P Q in (a) in K-map for Carry out Carry = PQ + Carry P + Carry Q out in in (b) Figure 6.13 K-map of full subtractor From the derived expressions, we may now construct the circuit of the full subtractor, which is presented in Figure This circuit may be compared with the circuit of the full adder presented in Figure 6.3. The reader may note that the only difference is the inclusion of one NOT gate in the full-subtractor circuit. Y Carry out Carry in P Q Figure 6.14 Circuit for full subtractor The method of binary subtraction we have followed here may be designated as the direct method. However, this is not the only method for binary subtraction. In the following section, we discuss about another popular method for binary subtraction.

18 210 Digital Electronics Time to Take a Test Redesign the full-subtractor circuit using two half subtractors and logic gates s Complement System The reader may recall that in Chapter 2 (see Section 2.7.2), we have introduced 2 s complement method of sign representation. In that section, through one example (5 4 = 1) we have indicated that one of the advantages of 2 s complement format is that it is capable of performing subtraction by addition. Let us consider another example here. Let us calculate 14 3 when both are in decimal. As per our method, we first calculate 1 s complement of the number to be subtracted. The binary equivalent of 3 is 0011 (in 4-bit format) and its 1 s complement is To calculate its 2 s complement, we add 1 to it or, in other terms, increment it by 1. In that case, 1100 becomes We will add this 1101 to the binary equivalent of 14, which is Now, gives us 1011 with carry as 1. The decimal equivalent of 1011 is 11, which is the correct result of the subtraction (14 3 = 11). The reader may ask a question here that what will be the outcome of 3 14 if both are in decimal. In this case, the result should be 11 in decimal. Let us see what happens if we adopt the same procedure of 2 s complement addition. As the binary equivalent of 14 is 1110, therefore, its 1 s complement is 0001 and its 2 s complement is When this is added to the binary equivalent of 3, that is, 0011, the result of the binary addition is 0101, with no carry. Now, the decimal equivalent of 0101 is 5. We expected to obtain the result of 11 in decimal. Then where have we gone wrong? We are not wrong. The answer we have obtained is correct, but in 2 s complement form. To convert it into its normal form, we first subtract 1 from it, making it 0100, and then complement it, which gives Note that 1011 in binary is 11 in decimal. So, our procedure was correct. Only thing remains is to correctly interpret it. The rules for interpreting the result of subtraction using 2 s complement method are as follows: (i) If there is a carry-out after 2 s complement addition, the result is positive. Neglect the carry. (ii) If there is no carry after 2 s complement addition, the result is negative and is in its 2 s complement form. Convert it into its normal binary form to get the absolute value without its sign. Reader, Remember! The interpretation of 2 s complement addition is very important. If carry is not generated, it becomes even more important. Recall Sherlock Holmes famous comment about curious behavior of dogs regarding the missing horse case. Answer to TTTT: A P Q Half subtractor Y C o P Q Half subtractor Y C o A C out C in

19 Digital Arithmetic s Complement Constructing a circuit to perform 1 s complement of any binary input is rather easy. Assuming a group of four binary digits, we incorporate four NOT gates for this purpose, as shown in Figure In this case, 4-bit input (D 0 D 3 ) will be complemented at the output as 0 3. Complemented 4-bit output D 3 D 2 D 1 D 0 D 3 D 2 D 1 D 0 4-bit input Figure 6.15 Circuit for 1 s complement (4-bit) s Complement After obtaining 1 s complement, 2 s complement may be obtained by adding 1 to it. For this purpose, any adder may be used, and if the input is available in a group of four bits, 4-bit full adders such as 7483 might be used. The relevant circuit for 2 s complement is shown in Figure 's complement output S 3 S 2 S 1 S 0 C out 4-bit binary full adder A 3 A 2 A C in V cc D 3 D 2 4-bit input D 1 D 0 Figure 6.16 Circuit for 2 s complement (4-bit) In Figure 6.16, we may note that the complemented input (D 0 D 3 ) is fed to one of the 4-bit inputs (A 0 A 3 ) of the 4-bit full adder, and other 4-bit input of the adder is connected with the ground to input zero. The C in input is connected with V cc so that 1 is added to the complemented input. The final output is available from S 0 S 3. Note that C out = 1 to be neglected.

20 212 Digital Electronics? Confusion Clearing Corner The term 2 s complement indicates either the operation (complement and add one) or the format (sign-bit representation, 2 s complement representation). Generally, the context will clarify the doubt regarding the usage. Time to Take a Test In the light of 1 s complement and 2 s complement, express 9 s complement and 10 s complement Subtraction with 2 s Complement Once we are ready to implement 2 s complement circuit, the remaining part of the circuit is an easier one. The complete circuit capable of 2 s complement subtraction is shown in Figure Note that this arrangement is capable of computing A, both and A operators being 4-bit. The circuit also considers any eventual carry generated from the previous modules. For the first module, the carry-in input of the top-adder should be grounded. 4-bit output with carry S 3 S 2 S 1 S 0 C out 4-bit binary full adder A 3 A 2 A C in C in bit input 0 S 3 S 2 S 1 S 0 C out 4-bit binary full adder A 3 A 2 A C in V cc Figure 6.17 A 3 A 2 A 0 4-bit input A 4-bit subtraction using 2 s complement for A Answer to TTTT: To obtain 9 s complement, substract each decimal digit from decimal 9. Add one to it to generate 10 s complement.

21 Digital Arithmetic ALU Integrated Circuits Integrated circuits are commercially available to perform various arithmetic and logical operations described in this chapter and also in Chapter 3. These ICs are designated as arithmetic logic unit (ALU). Generally, these ALUs function with 4-bit operators. However, they might be cascaded for wider operators. IC is such an ALU capable of performing arithmetic and logical operations with 4-bit operators. Observe that this IC is based on combinational logic and not on the sequential logic. Its pin and signal diagram is presented in Figure Note that this 24-pin IC accepts two 4-bit inputs, namely A 0 A 3 and 0 3, along with a carry input C n. The 4-bit result is available through F 0 F 3 along with a carry-out bit C n V cc A S S A 2 S S bit 19 A 3 7 ALU 18 C n 3 m 8 17 G F C n +4 F P F A= GND F 3 Figure 6.18 Pins and signals of (4-bit ALU) (Courtesy: Texas Instruments) Reader, Remember! As multiplication and division operations need clock pulses, which makes the circuit a sequential one, these functions are not available in the ALU because it is based on combinational logic. Its select input S 0 S 3 selects one of the sixteen functions for any one of the two modes, logical or arithmetic, which is decided by the condition of the external input m. A special output A = indicates that both the input parameters are equal in magnitude. The G and P outputs indicate carry look ahead status. The functional block diagram of is presented in Figure 6.19.

22 214 Digital Electronics V cc Data in Select C n m 4-bit ALU C n +4 A0 A3 F0 F A = S S G P Result out Status GND Figure 6.19 Functional block diagram of ALU? Confusion Clearing Corner A = output is necessary for cascading multiple for comparison operation. G and P outputs are necessary for carry look ahead during cascading. Table 6.8 shows all arithmetic (m = 0) and logical (m = 1) functional details for each select input (S 0 S 3 ). The reader may note that the arithmetic addition and subtraction are indicated by plus and minus, respectively, while the logical OR operation is denoted by +sign to distinguish between the two. A denotes A AND. Table 6.8 Select function for ALU Selection S 3 S 2 S 1 S 0 m = 1 (logical) Active-low data m = 0 (arithmetic) C n = 0 C n = F = A F = A minus 1 F = A F = A F = A minus 1 F = A F = A + F = A minus 1 F = A F = 1 F = minus 1 (2 s complement) F = zero F = A + F = A plus (A + ) F = A plus (A + ) plus F = F = A plus (A + ) F = A plus (A + ) plus F = A F = A minus minus 1 F = A minus (Contd.)

23 Digital Arithmetic F = A + F = A + F = (A + ) plus F = A F = A plus (A + ) F = A plus (A + ) plus F = A F = A plus F = A plus plus F = F = A plus (A + ) F = A plus (A + ) plus F = A + F = (A + ) F = (A + ) plus F = 0 F = A plus A F = A plus A plus F = A F = A plus A F = A plus A plus F = A F = A plus A F = A plus A plus F = A F = A F = A plus 1 IC is capable of handling 4-bit data. However, it may be cascaded to handle wider data sets, if felt necessary. The reader may note that its C n + 4 output (carry-out) is of open-collector type and needs an external pull-up resistor for proper output indication. Reader, Remember! If the reader is constructing a circuit with 74181, then one 10K pull-up resistor is to be connected between V cc and pin 16 of Digital Comparator Comparators perform the comparison of magnitudes of two inputs. When both inputs are analog, it is called an analog comparator. On the other hand, if both inputs are digital, then it is designated as a digital comparator. Digital comparators are simpler in operation and design, having three types of outputs, namely A =, A <, and A >, when A and are the input data. Depending upon the input conditions, one of these three output indicates HIGH (1) or true, while the remaining two indicate LOW (0) or false. Therefore, when both inputs are of 1-bit, the truth table of a comparator will be as shown in Table 6.9. Table 6.9 Truth table for a 1-bit comparator Input Output A A > A < A = From this truth table, we can generate the K-maps for A <, A =, and A >, and then design the circuit to perform the comparison operation, as shown in Figure 6.20.

24 216 Digital Electronics A A< A= A> Figure 6.20 Circuit for a 1-bit comparator? Confusion Clearing Corner Throughout the section of comparator, we are assuming all the inputs to be in unsigned binary integer form and never in 2 s complement form Cascading Inputs Using the same principle, we may design a 2-bit comparator or a 4-bit comparator. Commercially, 4-bit comparator ICs are available from different manufacturers. For wider input data such as 8-bit or 16-bit, the 4-bit comparator ICs may be used in cascade. For this purpose, cascading inputs are also provided in these ICs. To understand the principle of cascading, we may cascade two 1-bit comparators. Schematically, it is presented through Figure A> A> A> A> V cc A< A= cascade input data-in A Output A< A= A< A= cascade input data-in A Output A< A = A Figure 6.21 Schematic of cascaded pair of 1-bit comparators Truth Table for 1-it Comparator with Cascading Inputs The reader may note that in Figure 6.21, all three outputs from the lower comparator (for LS, at left) become cascading inputs for the higher comparator (for MS, at right). Therefore, the comparator is to first

25 Digital Arithmetic 217 investigate its own data-in, and if they are equal (A = ), then only the cascading inputs will be considered by it. We may now prepare the truth table for this 1-bit comparator with the cascading inputs, which is presented in Table Table 6.10 Truth table for a 1-bit comparator with cascading inputs Data inputs Cascading inputs Outputs A A > A < A = A > A < A = Initial Design We now proceed to design the circuit from this truth table. Although initially the truth table seems to be complex, we may simplify it through our careful observations. First, we observe that if A = 0 and = 1, then the output will always be A < = 1, without any influence of the three cascading inputs. This allows us to replace the logic values of the cascading inputs of these three rows by the don t-care symbol. Secondly, we observe that the same logic is applicable for A = 1 and = 0 input conditions. In this case also the cascading inputs do not matter and the output becomes A > = 1. Therefore, another three rows will contain the symbol for the cascading inputs. We now present the modified truth table in Table 6.11 after incorporating the outcome of these two observations. Table 6.11 Truth table for 1-bit comparator with cascading inputs (modified) Data inputs Cascading inputs Outputs A A > A < A = A > A < A = (Contd.)

26 218 Digital Electronics As the 4th, 5th, and 6th rows of the table are identical, therefore, we may delete the 5th and 6th rows from the table, keeping only the 4th row. Similarly, the 8th and 9th rows may also be deleted, as they are similar to the 7th row of the table. This modified table is presented in Table Observe that now the rows are less in number. Table 6.12 Truth table for 1-bit comparator with cascading inputs (further modified) Data inputs Cascading inputs Outputs A A > A < A = A > A < A = Now, let us observe the first three and the last three rows of the table. These rows deal with equality condition of A and data inputs. If both A and are 0s or both A and are 1s, then the present cascading inputs become the output. Therefore, we may formulate our first expression for design as If both the data inputs are equal, then the output will be the cascading input. Our second expression for design is If A = 0 and = 1, then the output will be A < = 1 (A > = 0, A = = 0). Our third and final expression for design is If A = 1 and = 0, then the output will be A > = 1 (A < = 0, A = = 0) Detailed Design Step 1 So we are now successful to compress Table 6.10 into the above three design expressions. To start our design, we take up the equality condition (the first expression). To generate the condition A = for all inputs of A and, we may use a XNOR gate. The reader may be curious about this decision. Why not a XOR gate in this case? The answer is, we need logic 1 condition at the output when both data inputs (A and ) are 1, for further processing, to be discussed in step 3. If we use a XOR gate, then we will get logic 0 as the output for equality condition. We may now present the initial stage of our circuit in Figure The reader may note that in Figure 6.22, we have shown all inputs and all outputs apart

27 Digital Arithmetic 219 from the XNOR gate. The relevant circuit for the remaining part will be discussed and completed step by step. A= A= A< A> A< A> A Figure 6.22 Circuit for 1-bit comparator with cascading inputs (step 1) Step 2 We may now look at the second and third design expressions. If data inputs are A = 0 and = 1, then the output will be A < = 1. On the other hand, if data inputs are A = 1 and = 0, then the output will be A > = 1. Using two NOT gates and two 2-input AND gates, we can complete this part of the circuit, and this stage of circuit design is presented in Figure A= A = A< A> A < A > A Figure 6.23 Circuit for 1-bit comparator with cascading inputs (step 2) Step 3 We now take up the further processing part, which we have indicated in step 1. From Table 6.12, we can observe that if the data inputs A and are equal in magnitude (indicated by the output of the XNOR gate), then the output will be the same as that of the cascading input (one of three). To implement

28 220 Digital Electronics this condition, we can place three more 2-input AND gates in the circuit. One of the two inputs of each of these three AND gates will be the output from the XNOR gate. Three cascading inputs will be other three inputs of these three AND gates. This design will generate the outputs A >, A <, and A =. Note that the first two outputs need further processing. However, the third one we may accept as one of the three final outputs. The condition of our yet to be finished circuit is shown in Figure A= A= A < A > A< A> A Figure 6.24 Circuit for 1-bit comparator with cascading inputs (step 3) Step 4 In this fourth and the final step of our design, we note that using the data inputs A and, we have already obtained (in step 2) one set of A > and A < outputs as shown in Figure In step 3, we left a pair of outputs, A > and A <, for further processing. Now, it is the time to logically OR both the sets of outputs to generate the final A > and A < outputs. Using two 2-input OR gates, we complete that part and also complete the present circuit design, as shown in Figure A= A= A< A> A< A> A Figure 6.25 Circuit for 1-bit comparator with cascading inputs (step 4)

29 Digital Arithmetic 221 The reader is now encouraged to check and verify whether the designed circuit will function properly or not bit Comparator 74LS85 ICs for multi-bit comparison are commercially available. 74LS85 is one of such ICs, which can perform 4-bit comparison and may be cascaded for operation with more number of bits as it offers cascading inputs. Pin and signal details of 74LS85 are shown in Figure V cc A< 2 15 A 3 Cascade input Output A= A> A> A= LS A 2 1 A< 7 10 A 0 GND Figure 6.26 Pins and signals of 74LS85 (4-bit comparator) The truth table for 74LS85 is presented in Table The reader may note that its last three rows indicate special cascading input conditions. Table 6.13 Truth table for 74LS85 Comparing inputs Cascading inputs Outputs A 3, 3 A 2, 2, 1 A 0, 0 A > A < A = A > A < A = A 3 > 3 H L L A 3 < 3 L H L A 3 = 3 A 2 > 2 H L L A 3 = 3 A 2 < 2 L H L A 3 = 3 A 2 = 2 > 1 H L L A 3 = 3 A 2 = 2 < 1 L H L A 3 = 3 A 2 = 2 = 1 A 0 > 0 H L L A 3 = 3 A 2 = 2 = 1 A 0 < 0 L H L A 3 = 3 A 2 = 2 = 1 A 0 = 0 H L L H L L (Contd.)

30 222 Digital Electronics A 3 = 3 A 2 = 2 = 1 A 0 = 0 L H L L H L A 3 = 3 A 2 = 2 = 1 A 0 = 0 L L H L L H A 3 = 3 A 2 = 2 = 1 A 0 = 0 H L L H A 3 = 3 A 2 = 2 = 1 A 0 = 0 H H L L L L A 3 = 3 A 2 = 2 = 1 A 0 = 0 L L L H H L 6.7 Solved Examples Example 6.1 Design a circuit to perform the 8-bit addition of unsigned binary integers. Using the designed circuit as an example, show the result of addition of to Sol. The circuit may be developed by using two bit adder ICs, as shown in Figure Note that the right-side adder handles the least significant 4 bits, while the left one takes care of the most significant 4 bits along with the carry. The carry input of the lower adder (C 0, pin 13) is to be connected with the system reference ground to input logic 0 for all cases of addition. V V C 4 V cc 12 GND S 4 S 3 S 2 S 1 C A 4 A 3 A bit binary adder Figure GND C 4 S 4 S 3 S 2 S 1 V cc bit binary adder C A 4 A 3 A bit parallel binary adder = Each of the unsigned binary operators of the present problem is divided into two parts: the lower four bits are fed to the right-sided lower adder and the higher four bits to the left-side adder. Cascading is completed by connecting the carry-out signal of the lower adder (pin 14) with the carry-in input of the higher adder (pin 13). The V cc input for both ICs has to be connected with a +5 V dc supply. The result of addition of the given operators will be available through S outputs of the devices along with carry-out from pin 14 of the left-sided adder. Example 6.2 Design a circuit for 2-digit CD addition and then indicate how 97 added to 53 will produce the result.

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