Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Transcription

1 Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits

2 Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension (1D) or multiple dimensions Chapter 5 2

3 A n-1 B n-1 A 1 B 1 A 0 B 0 X n X n-1 Y n-1 X 2 Y 2 Cell n-1 Cell 1 Y n X 1 Y 1 Cell 0 X 0 Y 0 C n-1 Example: n = 32 Number of inputs =? Truth table rows =? Equations with up to? input variables Equations with huge number of terms Design impractical! Iterative array takes advantage of the regularity to make design feasible C 1 C 0 Chapter 5 3

4 Binary addition used frequently Addition Development: Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance. Chapter 5 4

5 A 2-input, 1-bit width binary adder that performs following computations: X Y C S A half adder adds two bits to produce a two-bit sum sum is expressed as a X Y C S sum bit, S and a carry bit, C half adder can be specified as a truth table for S and C Chapter 5 5

6 K-Map for S, C is: This is a pretty trivial map! By inspection: S Y C Y 0 1 S = X Y + X Y = X Y X X S = (X + Y) (X + Y) and C = C = X Y ( ( X Y) ) These equations lead to several implementations. Chapter 5 6

7 derive following sets of equations for a half-adder: (a) S = X Y + X Y (d) S = (X + Y) C C = X Y C = (X + (b) S = (X + Y) (X + Y) (e) S C = X Y = Y) X Y C = X Y (c) S = ( C+ X Y ) C = X Y Chapter 5 7

8 The most common half adder implementation is: X Y S (e) S = X Y C = X Y C A NAND only implementation is: S = (XC + YC) C = X Y X Y C S Chapter 5 8

9 full adder is similar to a half adder, but includes a carry-in bit from lower stages, computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, same as half-adder: For a carry- in (Z) of 1: Z X Y C S Z X Y C S Chapter 5 9

10 Full-Adder Truth Table: Full-Adder K-Map: X Y Z C S S Y C Y X X Z Z Chapter 5 10

11 From K-Map, we get: S = X Y Z + X Y Z + X Y Z + C = X Y + X Z + Y Z S function is three-bit XOR function (Odd Function): S = X C is 1 if both X and Y are 1 (sum is 2), or if sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as: C = Y Z X Y (X Y) Z term X Y is carry generate. term X Y is carry propagate. + X Y Z Chapter 5 11

12 Full Adder Schematic Here X, Y, and Z, and C (from previous pages) are A, B, C i and C o, respectively. Also, G = generate and P = propagate. Co is a combination of 3-bit odd function (for S) and Carry logic (for C oi ): C i+1 G i (G = Generate) OR (P =Propagate AND C i = Carry In) Co = G + P Ci A i B i S i P i C i Chapter 5 12

13 To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i + 1 Description Subscript Name Carry In C i Augend A i Addend B i Sum S i Carry out C i+1 Chapter 5 13

14 Four-bit Ripple Carry Adder : four 1-bit Full Adders: B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 FA C 3 C 2 C 1 FA FA FA C 0 C 4 S 3 S 2 S 1 S 0 Chapter 5 14

15 One problem with addition of binary numbers is length of time to propagate ripple carry from the least significant bit to the most significant bit. gate-level propagation path for a 4-bit RCA A 3 B3 A 2 A 1 A 0 B 2 B 1 B 0 C 3 C 2 C 1 C 0 C 4 S 3 S 2 S 1 S 0 Note: "long path" is from A 0 or B 0 though circuit to S 3. Chapter 5 15

16 Given Stage i from a Full Adder, we know that there will be a carry generated when A i = B i = "1", whether or not there is a carry-in. A i B i Alternately, there will be G i a carry propagated if half-sum is "1" and a carry-in, C i occurs. two signal conditions P i are called generate, denoted as G i, and propagate, denoted as P i respectively and are identified in circuit: C i+1 S i C i Chapter 5 16

17 Gi, Pi, Si, and Ci are local to each cell of adder Defining equations for Full Adder in term of P i and G i : S i = Pi Ci Ci+ 1 = Gi + Pi Ci P = A B G = i 4 bit CLA : 2-level i i C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 (G 1 + P 1 G 0 + P 1 P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 i A i B i C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Chapter 5 17

18 Chapter 5 18

19 Chapter 5 19 Figure 5-6 in text shows implementation of these equations for four bits. This could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible. Instead, concept is extended another level by considering group generate (G 0-3 ) and group propagate (P 0-3 ) functions: Using these two equations: four 4-bit CLA adders 16 bits CLA P P P P P G P P P G P P G P G G = = C P G C + =

20 Specifications: 16-bit CLA Delays: NOT = 1 XOR = Isolated AND = 3 AND-OR = 2 Longest Delays: 3 CLA CLA CLA CLA 2 CLA Ripple carry adder* = = 36 CLA = = *See slide 16 Chapter 5 20

21 for n bit subtraction Subtract subtrahend N from minuend M If no end borrow occurs, then M N, result is a non-negative number and correct. If end borrow occurs, N > M and difference M N + 2 n is subtracted from 2 n, and a minus sign is appended to result. <- take 2 s complement ( ) 0011 Examples: Chapter 5 21

22 subtraction, 2 n N, is taking 2 s comp. of N To do both unsigned addition and unsigned subtraction requires: A B Shared simpler logic for both addition and subtraction Binary adder Borrow Complement Binary subtractor Selective 2's complementer Subtract/Add S 0 1 Quadruple 2-to-1 multiplexer Result Chapter 5 22

23 Two complements: Diminished Radix Complement of N (r 1) s complement for radix r 1 s complement for radix 2 Defined as (r n 1) Ν Radix Complement r s complement for radix r 2 s complement in binary Defined as r n N Subtraction is done by adding complement of subtrahend If result is negative, takes its 2 s complement Chapter 5 23

24 For r = 2, N = , n = 8 (8 digits): (r n 1) = = or 's complement of is then: Since 2 n 1 factor consists of all 1's and since 1 0 = 1 and 1 1 = 0, one's complement is obtained by complementing each individual bit (bitwise NOT). Chapter 5 24

25 For r = 2, N = , n = 8 (8 digits), we have: (r n ) = or 's compl of is then: s compl = 1's compl + 1, a fact that can be used in designing hardware Chapter 5 25

26 Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: Copy all least significant 0 s Copy the first 1 Complement all bits thereafter. 2 s Complement Example: Copy underlined bits: 100 and complement bits to the left: Chapter 5 26

27 For n-digit, unsigned numbers M and N, find M N : Add 2's compl of subtrahend N to minuend M: M + (2 n N) = M N + 2 n If M > N, sum produces end carry r n which is discarded; from above, M N remains. If M < N, sum does not produce an end carry and, is equal to 2 n ( N M ), 2's compl of ( N M ). To obtain result (N M), take 2's compl of sum and place to its left. Chapter 5 27

28 Find s comp carry of 1 indicates that no correction of result is required. Chapter 5 28

29 Find s comp carry of 0 indicates that a correction of result is required. Result = ( ) 2 s comp Chapter 5 29

30 For n-digit, unsigned numbers M and N, find M N in base 2: Add 1's compl of subtrahend N to minuend M: M + (2 n 1 N) = M N + 2 n 1 If M > N, result is excess by 2 n 1. The end carry 2 n when discarded removes 2 n, leaving a result short by 1. To fix this shortage, whenever and end carry occurs, add 1 in the LSB position. This is called the end-around carry. If M < N, sum does not produce an end carry and, is equal to 2 n 1 ( N M ), 1's compl of ( N M ). To obtain result (N M), take 1's compl of sum and place to its left. Chapter 5 30

31 Find s comp end-around carry occurs. Chapter 5 31

32 Find s comp carry of 0 indicates that a correction of result is required. Result = ( ) 1 s comp Chapter 5 32

33 Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers. To represent a sign (+ or ) we need exactly one more bit of information (1 binary digit gives 2 1 = 2 elements which is exactly what is needed). Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit: s a n 2 a 2 a 1 a 0 where: s = 0 for Positive numbers s = 1 for Negative numbers and a i = 0 or 1 represent magnitude. Chapter 5 33

34 Signed-Magnitude here n 1 digits are interpreted as a positive magnitude. Signed-Complement here digits are interpreted as rest of compl of number. There are two possibilities here: Signed 1's Complement Uses 1's Complement Arithmetic Signed 2's Complement Uses 2's Complement Arithmetic Chapter 5 34

35 r =2, n=3 Number Sign -Mag. 1's Comp. 2's Comp Chapter 5 35

36 If parity of three signs is 0: 1. Add magnitudes. 2. Check for overflow (a carry out of MSB) 3. sign of result is same as sign of the first operand. If parity of three signs is 1: 1. Subtract second magnitude from the first. 2. If a borrow occurs: take two s compl of result and make result sign compl of sign of the first operand. 3. Overflow will never occur. Chapter 5 36

37 Example 1: Example 2: Example 3: Chapter 5 37

38 Addition: 1. Add numbers including sign bits, discarding a carry out of the sign bits (2's Compl), or using an end-around carry (1's Compl). 2. If sign bits were the same for both numbers and sign of result is different, an overflow has occurred. 3. sign of result is computed in step 1. Subtraction: Form compl of number you are subtracting and follow rules for addition. Chapter 5 38

39 2 s compl examples Example 1: s compl examples Example 1: Example 2: Example 2: Chapter 5 39

40 Subtraction can be done by addition of 2's Compl. 1. Complement each bit (1's Complement.) 2. Add 1 to result. circuit shown computes A + B and A B: For S = 1, subtract, B 2 s compl 3 of B is formed by using XORs to form 1 s compl and adding 1 applied to C 0. C For S = 0, add, B is 3 passed through C S unchanged 4 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 2 C 1 C 0 FA FA FA FA S 2 S 1 S 0 S Chapter 5 40

41 Overflow occurs if n + 1 bits are required to contain result from an n-bit addition or subtraction Overflow can occur for: Addition of two operands with the same sign Subtraction of operands with different signs carry 0 1 carry Simplest way to implement overflow V = C n + C n 1 Chapter 5 41

42 binary digit multiplication table is trivial: (a b) b = 0 b = 1 a = This is simply Boolean AND function. a = Form larger products the same way we form larger products in base 10. Partial products are: 237 9, 237 4, and partial product summation for n digit, base 10 numbers requires adding up to n digits (with carries). n m digit multiply generates up to an m + n digit result Chapter 5 42

43 We execute radix 2 multiplication by: Computing partial products, and Justifying and summing partial products. (same as decimal) To compute partial products: Multiply row of multiplicand digits by each multiplier digit, one at a time. With binary numbers, partial products are very simple! They are either: all zero (if the multiplier digit is zero), or same as the multiplicand (if the multiplier digit is one). Note: No carries are added in partial product formation! Chapter 5 43

44 Partial products are: 101 1, 101 1, and partial product summation for n digit, base numbers requires adding up to n digits (with carries) in a column. n m digit multiply generates up to an m + n digit result (same as decimal) Chapter 5 44

45 We can also make an n m block multiplier and use that to form partial products. Example: 2 2 logic equations for each partial-product binary digit are shown below: "add" columns to get product bits P0, P1, P2, and P3. Note that some columns may generate carries. b 1 b 0 a 1 a 0 (a 0. b 1 ) (a 0. b 0 ) + (a 1. b 1 ) (a 1. b 0 ) P 3 P 2 P 1 P 0 Chapter 5 45

46 A 0 B 1 B 0 A 1 B 1 B 0 HA HA C 3 C 2 C 1 C 0 Chapter 5 46

47 Chapter 5 47

48 Chapter 5 48

49 Another way to implement multipliers is to use an n m cellular array structure of uniform elements as shown: Each element computes a single bit product equal to a i b j, and implements a single bit full adder Column Sum from above Cell [ j, k ] pp [ j, k ] Carry [ j, k ] AB Co Ci FA S b[ k ] Column Sum to below a[ j ] Carry [ j, (k - 1)] Chapter 5 49

50 Chapter 5 50

51 Chapter 5 51

52 Contraction of a ripple carry adder to incrementer for n = 3 Set B = 001 C 3 5 X X X A A 1 A C 1 3 C S 2 S 1 S 0 (a) A 2 A 1 A 0 S 2 S 1 S 0 (b) The middle cell can be repeated to make an incrementer with n > 3. Chapter 5 52

53 Incrementing Adding a fixed value to an arithmetic variable Fixed value is often 1, called counting (up) Examples: A + 1, B + 4 Functional block is called incrementer Decrementing Subtracting a fixed value from an arithmetic variable Fixed value is often 1, called counting (down) Examples: A 1, B 4 Functional block is called decrementer Chapter 5 53

54 Chapter 5 54

55 B 3 B 2 B 1 B C 5 C 4 C 3 (a) C 2 C 1 C 0 B 3 0 B 2 0 B 1 B 0 C 3 C 2 C 1 C 0 C 2 1 C 2 2 (b) Chapter 5 55

56 Chapter 5 56

57 Extension - increase in the number of bits at the MSB end of an operand by using a complement representation Copies the MSB of the operand into the new positions Positive operand example extended to 16 bits: Negative operand example extended to 16 bits: Chapter 5 57