1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple carry adder can be split into three parts: the first bit, the middle six bits, and the last bit. For the first bit, the critical path for the c out is one XOR, one AND, and one OR gate. Then for the next 6 bits, since p has had plenty of time to be computed already, we need only one AND and one OR gate to get from c in to c out. In the final stage, the important path is from c in to the s output, which is one XOR delay. Therefore, the delays are: t first = 0.5*2 2 *t p + 2*0.25*2 2 *t p = 4t p t middle = 2*0.25*2 2 *t p = 2t p t last = 0.5*2 2 *t p = 2t p t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 8t p B The CLA logic functions implemented are c o3 = g 3 + p 3 g 2 +p 3 p 2 g +p 3 p 2 p g 0 +p 3 p 2 p p 0 c in c o2 = g 2 + p 2 g + p 2 p g 0 + p 2 p p 0 c in c o = g + p g 0 + p p 0 c in c o0 = g 0 + p 0 c in cin 4bit CLA c o3 4bit CLA Figure. Carry look-ahead architecture. For the first 4-bit CLA group, the important path is from c in to c o3. After one XOR delay, all the g i s and p i s are computed. In the most straightforward implementation, the worst-case path is then through one 5-input AND gate and a 5-input OR gate (other topologies are possible) which takes a total of: t firstcla = 0.5*2 2 *t p *5 2 *t p *5 2 *t p = 4.5t p For the second 4-bit CLA group, the important path is from c in to c o2 to the final sum bit. Again using the most straightforward implementation, c in to c o2 takes one 4-input AND gate and one 4- input OR gate. From c o2 to sum goes through one XOR gate: t secondcla = 0.25*4 2 *t p *4 2 *t p + 0.5*2 2 *t p = 0t p The total delay is then the sum of these two groups: t total_cla8 = t firstcla + t secondcla = 24.5t p C In the analysis of a 32-bit ripple carry adder, the same delays calculated for the 8-bit case can be reused:

2 t total_ripple32 = t first + 30*t middle + t last = 4t p + 30*2t p + 2t p = 66t p For the 32-bit CLA using a hierarchical propagate/generate scheme, refer to the figure for the worst-case path through the entire adder. Calculate the sum bit 2t p +2t p Pass the carry back 2t p + 2t p Obtain p i,g i (2t p ) Obtain P,G block propagate generates 8t p +8t p It takes one XOR delay to get the propagate/generate terms for each bit, which is 2t p. The propagate/generate terms in the second- and third-levels are computed as: P middle = P top0 *P top *P top2 *P top3 G middle = G top3 + G top2 *P top3 + G top *P top3 *P top2 + G top0 *P top3 *P top2 *P top So the worst-case path to make these P and G terms is one 4-input AND gate followed by a 4- input OR gate, which totals 8t p for each level. Traversing back up the tree, the groups can compute their carry-outs using the simple c o = G + P*c i so it only takes one 2-input AND gate and one 2-input OR gate, which is 2t p for each level. Once the top level is reached, the final carry takes 2t p and the sum requires an additional 2-input XOR, adding another 2t p. Totaling all the delays yields a critical path delay of t total_cla32 = 2t p + (8t p + 8t p ) + (2t p + 2t p ) + (2t p + 2t p ) = 26t p As the as the number of bits increases, the carry look ahead adder has a distinct advantage. However, for adders with less than 0-bits, it is usually faster to implement the simpler ripple carry architecture.

3 2 Comparator design 2A The simplest implementation calculates the (B-A). If the resulting is negative (ie. if the sign bit is one), then A is greater than B. If the sign bit is zero, then A <= B. The implementation would simply bitwise complement B and compute OUT = A + (~B) +. The output of the N-bit comparator would simply be the last bit of this result, ie. OUT[N-]. A N B N N OUT OUT[N-] A>B Assuming the adder is a ripple carry adder, the worst case delay of the comparator would be of the same form as A: 4*t p +(N-2)*2t p +2*t p = (N+)*2t p

4 3 Signed Multiplication This solution implements Baugh-Wooley multiplier technique. As an illustrative example, extend the traditional binary notation to allow bits to be negative (similar to the carry-save technique). In this case, the failing example can be transformed to: Extended binary Decimal equivalent (-8)+4 = (-4) x (-8)+ = (-7) (-8)+4 = (-4) (0) (0) (-32)= (-32)+(-8)+4=28 So, this wacky method appears to give the correct answer (at least for this example). It is left as an exercise to prove that it works for all numbers. Now, consider how to implement this multiplier. In the general case, the following partial products are required (parentheses signify the negative weighted bits). (a 3 ) a 2 a a 0 (b 3 ) b 2 b b 0 (a 3 b 0 ) a 2 b 0 ab 0 a 0 b 0 (a 3 b ) a 2 b a b a 0 b (a 3 b 2 ) a 2 b 2 a b 2 a 0 b 2 a 3 b 3 (a 2 b 3 ) (a b 3 ) (a 0 b 3 ) P 7 p 6 p 5 p 4 p 3 p 2 p p0 The bits in the partial products can be reordered to form more useful groups consisting of positive and negative terms: (a 3 ) a 2 a a 0 (b 3 ) b 2 b b 0 a 2 b 0 ab 0 a 0 b 0 a 2 b a b a 0 b a 3 b 3 0 a 2 b 2 a b 2 a 0 b 2 (a 3 b 2 ) (a 3 b ) (a 3 b 0 ) (a 2 b 3 ) (a b 3 ) (a 0 b 3 ) P 7 p 6 p 5 p 4 p 3 p 2 p p 0 We are trying to add the positive partial products (above dashed line) and subtract the negative partial products (those below the dashed line). The negatively weighted partial products can be interpreted as two numbers that can be negated, allowing the whole array to be added together. Note that blank entries in the table are implicit zeros.

5 Consider the first negative row. Negation is tricky here because we only want to negate if a 3 is one. If a 3 is zero, we want the entire row to be zero. The logic function for each bit is then a 3 bi. For the entire number [0 0 (a 3 b 2 ) (a 3 b ) (a 3 b 0 )], the result would be the following sum: a 3 a b a a b a b a 3 where the extra a 3 terms sprinkled around are for sign-extension and for the + in the two s complement conversion. As another simplification, the leading two positions can be interpreted is either as: [0 0] = 0 [a 4 a 3 ] = [a 3 a 3 ] = [] = or equivalently as: [ a 4 ] + = [ a 3 ] + = [] + [ 0] + = 0 [0 0] = = [] a a 3 3 = 0 = If the above methods are also use to negate the partial products starting with b 3, the resulting the initial partial sum array would be: (a 3 ) a 2 a a 0 (b 3 ) b 2 b b 0 a 2 b 0 ab 0 a 0 b 0 a 2 b a b a 0 b a 3 b 3 0 a 2 b 2 a b 2 a 0 b 2 a a b a b a b b a b a b a b P 7 P 6 p 5 p 4 p 3 p 2 p p 0 Merging the constant one s together, yields the final partial sum array: a 3 b 3 0 a 2 b 2 a b 2 a 0 b 2 a a b a b a b b a b a b a b (a 3 ) a 2 a a 0 (b 3 ) b 2 b b 0 a 2 b 0 ab 0 a 0 b 0 a 2 b a b a 0 b P 7 P 6 p 5 p 4 p 3 p 2 p p 0

6 We can implement this array in the following way. Using the block below as the processing element of the main array we can obtain the result p[7:0] sin a sin a b b cout cin cout FA cin sout sout a2 a a0 b0 b b2 ~ ~b4 p7 p6 p5 p4 p3 p2 p p0