ALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1
|
|
- Barnard Gregory
- 6 years ago
- Views:
Transcription
1 ALUs and Data Paths Subtitle: How to design the data path of a processor. Copyright Joanne DeGroat, ECE, OSU 1
2 Lecture overview General Data Path of a multifunction ALU Copyright Joanne DeGroat, ECE, OSU 2
3 of ALUs and Data Paths Objective: a General Purpose Data Path such as the datapath found in a typical computer. A Data Path Contains: Registers general purpose, special purpose Execution Units capable of multiple functions Copyright Joanne DeGroat, ECE, OSU 3
4 ALU Operations Add (A+B) Add with (A+B+n) Subtract (A-B) Subtract with Borrow (A-B-n) [Subract reverse (B-A)] [Subract reverse with Borrow (B-A-n)] Negative A (-A) Negative B (-B) Increment A (A+1) Increment B (B+1) Decrement A (A-1) Decrement B (B-1) Logical AND Logical OR Logical XOR Not A Not B A B Multiply Step or Multiply Divide Step or Divide Mask Conditional AND/OR (uses Mask) Shift Zero Copyright Joanne DeGroat, ECE, OSU 4
5 A High Level Copyright Joanne DeGroat, ECE, OSU 5
6 The AMD 2901 Bit Slice ALU Copyright Joanne DeGroat, ECE, OSU 6
7 The Architecture Copyright Joanne DeGroat, ECE, OSU 7
8 Arithmetic Logic rcuits The Brute Force Approach A more modern approach Copyright Joanne DeGroat, ECE, OSU 8
9 Arithmetic Logic rcuits The Brute Force Approach AB AB A B A Cout A FA B n Function N to 1 Mux A more modern approach Copyright Joanne DeGroat, ECE, OSU 9
10 Arithmetic Logic rcuits The Brute Force Approach AB AB A B A Cout A FA B n Function N to 1 Mux A B A B A more modern approach S Logic Unit 2 to 1 Mux Arithmetic Unit Copyright Joanne DeGroat, ECE, OSU 10
11 A Generic Function Unit Desire a generic functional unit that can perform many functions A 4-to-1 mux will perform all basic logic functions of 2 inputs Copyright Joanne DeGroat, ECE, OSU 11
12 Low level implementation At the implementation Level the design can be With transmission gates Very important for VLSI implementation Implementation has a total Of 16 transistors. Copyright Joanne DeGroat, ECE, OSU 12
13 Low level implementation An implementation in pass gates (CMOS) When the control signal is a 1 the value will be transmitted Otherwise it is an open switch A B A B G(A,B) AB A+B AxorB G G G G Copyright Joanne DeGroat, ECE, OSU 13
14 Lets look at Binary Addition We can use this generic function unit construct a generic ALU. For Binary Addition consider the following: SUMi = Ai xor Bi xor +1 = + Ai + Bi A B n Sum Cout Copyright Joanne DeGroat, ECE, OSU 14
15 An Alternative - Define two signals Equations for P and K = Ai xor Bi = A B Now can reform equations into functions of P and K Copyright Joanne DeGroat, ECE, OSU 15
16 New functions Using these definitions of P and K SUMi = xor +1 = + = + AB You can use the generic functional blocks to generate P and K and then select the correct function for final output Copyright Joanne DeGroat, ECE, OSU 16
17 A bit slice of the ALU Slice starts out with a generic unit which can produce any function of inputs Ai and Bi to produce P Need another to produce K And a 3 rd to generate the result And also need a dedicated unit to compute the carry out, the +1 term +1 ll Copyright Joanne DeGroat, ECE, OSU 17
18 Generation of the carry out The carry chain is the critical path for arithmetic operations. A simple ripple carry circuit is shown here for the slice Actual implementation depend on the technology in which implemented. Copyright Joanne DeGroat, ECE, OSU 18
19 chain implementation CMOS Manchester carry chain using precharge pulldown logic works well. ECL look-ahead circuitry works well as ECL allows for large fan-in wired OR gates. Copyright Joanne DeGroat, ECE, OSU 19
20 Multibit implementation ll ll ll ll ll ll ll ll Copyright Joanne DeGroat, ECE, OSU 20
21 Function codes 0 NOR A B A AB B XOR A B A B G G G G G NAND AND XNOR B A +B A A+B OR 1 The G values for the various logic functions By setting the value of the G inputs the output is the Corresponding logic function of the data which comes in On the select inputs. Copyright Joanne DeGroat, ECE, OSU 21
22 Binary Subtraction Much like addition but now choose P = A xnor B K = A B Diff D = A xor B xor Bin = A xnor B xnor Bin Borrow Out Bout=P Bin + P K P K A B Bin Diff Bout Copyright Joanne DeGroat, ECE, OSU 22
23 The codes to have the ALU work Consider as we go to the sliced ALU Logic function done in the P generic unit Math used all the blocks Function P K R n A A and B OR A + B + n n A+B Incr A A B or Bin Copyright Joanne DeGroat, ECE, OSU 23
24 Multibit implementation ll ll ll ll ll ll ll ll Copyright Joanne DeGroat, ECE, OSU 24
CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19
More informationCMPUT 329. Circuits for binary addition
CMPUT 329 Parallel Adder with Carry Lookahead and ALU Ioanis Nikolaidis (Katz & Borriello) rcuits for binary addition Full adder (carry-in to cascade for multi-bit adders) Sum = xor A xor B Cout = B +
More informationVLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1
VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath
More informationECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH
More informationISSN (PRINT): , (ONLINE): , VOLUME-4, ISSUE-10,
A NOVEL DOMINO LOGIC DESIGN FOR EMBEDDED APPLICATION Dr.K.Sujatha Associate Professor, Department of Computer science and Engineering, Sri Krishna College of Engineering and Technology, Coimbatore, Tamilnadu,
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH
More informationEECS150. Arithmetic Circuits
EE5 ection 8 Arithmetic ircuits Fall 2 Arithmetic ircuits Excellent Examples of ombinational Logic Design Time vs. pace Trade-offs Doing things fast may require more logic and thus more space Example:
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:
More informationNTE74LS181 Integrated Circuit TTL Arithmetic Logic Unit/Function Generator
NTE74LS181 Integrated Circuit TTL Arithmetic Logic Unit/Function Generator Description: The NTE74LS181 is an arithmetic logic unit (ALU)/function generator in a 24 Lead DIP type package that has the complexity
More informationArithmetic Building Blocks
rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor Input-Output
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN
More informationARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
More informationMidterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.
Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits
More informationAdditional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationEFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS
INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS B. Venkata Sreecharan 1, C. Venkata Sudhakar 2 1 M.TECH (VLSI DESIGN)
More informationCombinational Logic Design Arithmetic Functions and Circuits
Combinational Logic Design Arithmetic Functions and Circuits Overview Binary Addition Half Adder Full Adder Ripple Carry Adder Carry Look-ahead Adder Binary Subtraction Binary Subtractor Binary Adder-Subtractor
More informationXOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.
XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special
More informationMenu. Binary Adder EEL3701 EEL3701. Add, Subtract, Compare, ALU
Other MSI Circuit: Adders >Binar, Half & Full Canonical forms Binar Subtraction Full-Subtractor Magnitude Comparators >See Lam: Fig 4.8 ALU Menu Look into m... 1 Binar Adder Suppose we want to add two
More informationIntroduction to CMOS VLSI Design Lecture 1: Introduction
Introduction to CMOS VLSI Design Lecture 1: Introduction David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Introduction Integrated circuits: many transistors
More informationECE/CS 250 Computer Architecture
ECE/CS 250 Computer Architecture Basics of Logic Design: Boolean Algebra, Logic Gates (Combinational Logic) Tyler Bletsch Duke University Slides are derived from work by Daniel J. Sorin (Duke), Alvy Lebeck
More information9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017
9. Datapath Design Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 2, 2017 ECE Department, University of Texas at Austin
More informationECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationModule 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops
Module 2 asic Digital uilding locks Lecturer: Dr. Yongsheng Gao Office: Tech 3.25 Email: Web: Structure: Textbook: yongsheng.gao@griffith.edu.au maxwell.me.gu.edu.au 6 lecturers 1 tutorial 1 laboratory
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates
ECE 250 / CPS 250 Computer Architecture Basics of Logic Design Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Andrew Hilton (Duke), Alvy Lebeck (Duke) Benjamin Lee (Duke), and Amir
More informationChapter 5 Arithmetic Circuits
Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed
More informationArithmetic Circuits-2
Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier
More informationHardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
More informationECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationHw 6 due Thursday, Nov 3, 5pm No lab this week
EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:30-8:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:30-8:00pm
More informationLogic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits
Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationCSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego
CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationNumber representation
Number representation A number can be represented in binary in many ways. The most common number types to be represented are: Integers, positive integers one-complement, two-complement, sign-magnitude
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28
More informationEE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
More information14:332:231 DIGITAL LOGIC DESIGN
4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Lecture #4: Adders, ubtracters, and ALUs Vector Binary Adder [Wakerly 4 th Ed., ec. 6., p. 474] ingle
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationCMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned
Focus Groups CMSC 33 Lecture 7 Need good sample of all types of CS students Mon /7 & Thu /2, 2:3p-2:p & 6:p-7:3p Announcement: in-class lab Thu /3 Homework 3 Questions Circuits for Addition Midterm Exam
More informationReview for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
MS 33 Lecture 8 Midterm Exam returned Assign Homework 3 ircuits for Addition Digital Logic omponents Programmable Logic Arrays UMB, MS33, Richard hang MS 33, omputer Organization & Assembly
More informationCSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design
CSE477 VLSI Digital Circuits Fall 22 Lecture 2: Adder Design Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477 [Adapted from Rabaey s Digital Integrated Circuits, 22, J. Rabaey et al.] CSE477
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationDESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNIT
International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNIT Rakshith Saligram 1
More informationEECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1
EECS5 - Digital Design Lecture - Combinational Logic Circuits Part Feburary 26, 22 John Wawrzynek Spring 22 EECS5 - Lec-cl Page Combinational Logic (CL) Defined y i = f i (x,...., xn-), where x, y are
More informationChapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design
Chapter 03: Computer Arithmetic Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design Objective To understand adder circuit Subtractor circuit Fast adder circuit 2 Adder Circuit 3 Full
More informationEECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.1-11.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a half-hour hour appointment with me to discuss your
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in
More informationL10 State Machine Design Topics
L State Machine Design Topics States Machine Design Other topics on state machine design Equivalent sequential machines Incompletely specified machines One Hot State Machines Ref: text Unit 15.4, 15.5,
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits
Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted
More informationBit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder
it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
More informationCombinational Logic Trainer Lab Manual
Combinational Logic Trainer Lab Manual Control Inputs Microprocessor Data Inputs ff Control Unit '0' Datapath MUX Nextstate Logic State Memory Register Output Logic Control Signals ALU ff Register Status
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationXI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.
2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two
More informationCarry Look Ahead Adders
Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More informationI. INTRODUCTION. CMOS Technology: An Introduction to QCA Technology As an. T. Srinivasa Padmaja, C. M. Sri Priya
International Journal of Scientific Research in Computer Science, Engineering and Information Technology 2018 IJSRCSEIT Volume 3 Issue 5 ISSN : 2456-3307 Design and Implementation of Carry Look Ahead Adder
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationWe are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 3 1 Logistics If you cannot login to MarkUs, email me your UTORID and name. Check lab marks on MarkUs, if it s recorded wrong, contact Larry within a week after the lab. Quiz 1 average: 86%
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationFull Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder
Outline E 66 U Resources: dders & Multipliers Full dder Ripple arry dder arry-look-head dder Manchester dders arry Select dder arry Skip dder onditional Sum dder Hybrid Designs leksandar Milenkovic E-mail:
More informationEECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) September 5, 2002 John Wawrzynek Fall 2002 EECS150 Lec4-bool1 Page 1, 9/5 9am Outline Review of
More informationOverview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples
Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationArithmetic Circuits-2
Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier
More informationOutline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined
EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) January 30, 2003 John Wawrzynek Outline Review of three representations for combinational logic:
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang Half dder Inputs: and Outputs:
More informationDesign of a Novel Reversible ALU using an Enhanced Carry Look-Ahead Adder
Design of a Novel Reversible ALU using an Enhanced Carry Look-Ahead Adder *K.JYOTHI **Md.ASIM IQBAL *M.TECH Dept Of ECE, KAKATHIYA UNIVERSITY OF ENGINEERING AND TECHNOLOGY **Asst. prof Dept of ECE, KAKATHIYA
More informationBinary addition by hand. Adding two bits
Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Overview Part 1 Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More informationPG - TRB UNIT-X- DIGITAL ELECTRONICS. POLYTECHNIC-TRB MATERIALS
SRIMAAN COACHING CENTRE-PG-TRB-PHYSICS- DIGITAL ELECTRONICS-STUDY MATERIAL-CONTACT: 8072230063 SRIMAAN PG - TRB PHYSICS UNIT-X- DIGITAL ELECTRONICS POLYTECHNIC-TRB MATERIALS MATHS/COMPUTER SCIENCE/IT/ECE/EEE
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationCMP 334: Seventh Class
CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative
More informationChapter 7. VLSI System Components
VLSI Design Chapter 7 VLSI System Components Jin-Fu Li Chapter 7 VLSI System Components Introduction Datapath Operators Memory Elements Control Structures 2 System-Level Hierarchy System (Top) Complex
More informationLecture A: Logic Design and Gates
Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:
More informationHomework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm
EE241 - Spring 2010 Advanced Digital Integrated Circuits Lecture 25: Digital Arithmetic Adders Announcements Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due
More informationLecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
More information1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationIntroduction to Computer Engineering ECE 203
Introduction to Computer Engineering ECE 203 Northwestern University Department of Electrical Engineering and Computer Science Teacher: Robert Dick Office: L477 Tech Email: dickrp@ece.northwestern.edu
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationHakim Weatherspoon CS 3410 Computer Science Cornell University
Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. memory inst 32 register
More informationCOMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHIC-LOGIC UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ
OMUTERS ORGANIZATION 2ND YEAR OMUTE SIENE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHI-LOGI UNIT JOSÉ GARÍA RODRÍGUEZ JOSÉ ANTONIO SERRA ÉREZ Tema 3. La Unidad entral de roceso. A.L.U. Arithmetic Logic Unit
More informationChapter 4: Designing Combinational Systems Uchechukwu Ofoegbu
Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0 s = sum c out carry-out a, b = added bits C = carry in a
More informationWhere are we? Data Path Design
Where are we? Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath Data Path Design
More informationCircuits & Boolean algebra.
Circuits & Boolean algebra http://xkcd.com/730/ CSCI 255: Introduction to Embedded Systems Keith Vertanen Copyright 2011 Digital circuits Overview How a switch works Building basic gates from switches
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More informationCS 140 Lecture 14 Standard Combinational Modules
CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier
More informationVHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES
VHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES 1.Devarasetty Vinod Kumar/ M.tech,2. Dr. Tata Jagannadha Swamy/Professor, Dept of Electronics and Commn. Engineering, Gokaraju Rangaraju
More informationReversible ALU Implementation using Kogge-Stone Adder
Reversible ALU Implementation using Kogge-Stone Adder K.Ravitejakhanna Student, Department of ECE SR Engineering College, Ch.Sridevi Reddy Asst.Professor, Department of ECE SR Engineering College, Abstract
More information