CprE 281: Digital Logic
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1 CprE 281: Digital Logic Instructor: Alexander Stoytchev
2 Fast Adders CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 HW5 is out Administrative Stuff It is due on Monday Oct 4pm. Please write clearly on the first page (in block capital letters) the following three things: Your First and Last Name Your Student ID Number Your Lab Section Letter Also, please staple all of your pages together.
4 Labs Next Week Administrative Stuff Mini-Project This one is worth 3% of your grade. Make sure to get all the points _Fall_281/labs/Project-Mini/
5 Quick Review
6 The problems in which row are easier to calculate? ?????? ??????
7 The problems in which row are easier to calculate? Why?
8 Another Way to Do Subtraction =
9 Another Way to Do Subtraction = = 82 (100 64) - 100
10 Another Way to Do Subtraction = = 82 (100 64) = 82 ( ) - 100
11 Another Way to Do Subtraction = = 82 (100 64) = 82 ( ) = 82 (99 64) 1-100
12 Another Way to Do Subtraction = = 82 (100 64) = 82 ( ) Does not require borrows = 82 (99 64) 1-100
13 9 s Complement (subtract each digit from 9)
14 10 s Complement (subtract each digit from 9 and add 1 to the result) = 36
15 Another Way to Do Subtraction = 82 (99 64) 1-100
16 Another Way to Do Subtraction 9 s complement = 82 (99 64) 1-100
17 Another Way to Do Subtraction 9 s complement = 82 (99 64) =
18 Another Way to Do Subtraction 9 s complement = 82 (99 64) = s complement
19 Another Way to Do Subtraction 9 s complement = 82 (99 64) = s complement =
20 Another Way to Do Subtraction 9 s complement = 82 (99 64) = s complement = // Add the first two. =
21 Another Way to Do Subtraction 9 s complement = 82 (99 64) = s complement = // Add the first two. = = 18 // Just delete the leading 1. // No need to subtract 100.
22
23 2 s complement Let K be the negative equivalent of an n-bit positive number P. Then, in 2 s complement representation K is obtained by subtracting P from 2 n, namely K = 2 n P
24 Deriving 2 s complement For a positive n-bit number P, let K 1 and K 2 denote its 1 s and 2 s complements, respectively. K 1 = (2 n 1) P K 2 = 2 n P Since K 2 = K 1 1, it is evident that in a logic circuit the 2 s complement can computed by inverting all bits of P and then adding 1 to the resulting 1 s-complement number.
25 Find the 2 s complement of
26 Find the 2 s complement of Invert all bits.
27 Find the 2 s complement of Then add 1.
28 Interpretation of four-bit signed integers [ Table 3.2 from the textbook ]
29 Interpretation of four-bit signed integers The top half is the same in all three representations. It corresponds to the positive integers.
30 Interpretation of four-bit signed integers In all three representations the first bit represents the sign. If that bit is 1, then the number is negative.
31 Interpretation of four-bit signed integers Notice that in this representation there are two zeros!
32 Interpretation of four-bit signed integers There are two zeros in this representation as well!
33 Interpretation of four-bit signed integers In this representation there is one more negative number.
34 Taking the 2 s complement negates the number decimal b 3 b 2 b 1 b 0 take the 2's complement b 3 b 2 b 1 b 0 decimal
35 Taking the 2 s complement negates the number decimal b 3 b 2 b 1 b 0 take the 2's complement b 3 b 2 b 1 b 0 decimal This is the only exception
36 Taking the 2 s complement negates the number decimal b 3 b 2 b 1 b 0 take the 2's complement b 3 b 2 b 1 b 0 decimal And this one too.
37 The number circle for 2's complement [ Figure 3.11a from the textbook ]
38 A) Example of 2 s complement addition ( 5) ( 2) ( 7) [ Figure 3.9 from the textbook ]
39 B) Example of 2 s complement addition ( 5) ( 2) ( 3) [ Figure 3.9 from the textbook ]
40 C) Example of 2 s complement addition ( 5) ( 2) ( 3) ignore [ Figure 3.9 from the textbook ]
41 D) Example of 2 s complement addition ( 5) ( 2) ( 7) ignore [ Figure 3.9 from the textbook ]
42
43 Naming Ambiguity: 2's Complement 2's complement has two different meanings: representation for signed integer numbers algorithm for computing the 2's complement (regardless of the representation of the number)
44 Naming Ambiguity: 2's Complement 2's complement has two different meanings: representation for signed integer numbers in 2's complement algorithm for computing the 2's complement (regardless of the representation of the number) take the 2's complement
45 Example of 2 s complement subtraction ( 5) ( 2) ( 3) ignore means take the 2's complement [ Figure 3.10 from the textbook ]
46 Example of 2 s complement subtraction ( 5) ( 2) ( 3) ignore Notice that the minus changes to a plus. means take the 2's complement [ Figure 3.10 from the textbook ]
47 Example of 2 s complement subtraction ( 5) ( 2) ( 3) ignore [ Figure 3.10 from the textbook ]
48 Example of 2 s complement subtraction ( 5) ( 2) ( 3) ignore [ Figure 3.10 from the textbook ]
49 Graphical interpretation of four-bit 2 s complement numbers [ Figure 3.11 from the textbook ]
50 Example of 2 s complement subtraction ( 5) ( 2) ( 7) ignore [ Figure 3.10 from the textbook ]
51 Example of 2 s complement subtraction ( 5) ( 2) ( 7) [ Figure 3.10 from the textbook ]
52 Example of 2 s complement subtraction ( 5) ( 2) ( 3) [ Figure 3.10 from the textbook ]
53 Take Home Message Subtraction can be performed by simply adding the 2 s complement of the second number, regardless of the signs of the two numbers. Thus, the same adder circuit can be used to perform both addition and subtraction!!!
54 Adder/subtractor unit y n 1 y 1 y 0 Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
55 XOR Tricks control out y
56 XOR as a repeater 0 y y
57 XOR as an inverter 1 y y
58 Addition: when control = 0 y n 1 y 1 y 0 Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
59 Addition: when control = 0 y n 1 0 y 1 0 y Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
60 Addition: when control = 0 y n 1 0 y 1 0 y Add Sub control x n 1 x 1 x 0 c n n -bit adder y n-1 y 1 y 0 c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
61 Subtraction: when control = 1 y n 1 y 1 y 0 Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
62 Subtraction: when control = 1 y n 1 1 y 1 1 y Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
63 Subtraction: when control = 1 y n 1 1 y 1 1 y Add Sub control x n 1 x 1 x 0 c n n -bit adder y n-1 y 1 y 0 c 0 s n 1 s 1 s 0 [ Figure 3.12 from the textbook ]
64 Subtraction: when control = 1 y n 1 1 y 1 1 y Add Sub control x n 1 x 1 x 0 c n n -bit adder y n-1 y 1 y 0 1 c 0 s n 1 s 1 s 0 carry for the first column! [ Figure 3.12 from the textbook ]
65 Examples of determination of overflow ( 7) ( 2) ( 7) ( 2) ( 9) ( 5) ( 7) ( 2) ( 7) ( 2) ( 5) ( 9) [ Figure 3.13 from the textbook ]
66 Examples of determination of overflow ( 7) ( 2) ( 7) ( 2) ( 9) ( 5) ( 7) ( 2) ( 7) ( 2) ( 5) ( 9) Include the carry bits: c 4 c 3 c 2 c 1 c 0
67 Examples of determination of overflow ( 7) ( 2) ( 7) ( 2) ( 9) ( 5) ( 7) ( 2) ( 7) ( 2) ( 5) ( 9) Include the carry bits: c 4 c 3 c 2 c 1 c 0
68 Examples of determination of overflow c 4 = 0 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 0 c 3 = 0 ( 9) ( 5) c 4 = 1 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 1 c 3 = 0 ( 5) ( 9) Include the carry bits: c 4 c 3 c 2 c 1 c 0
69 Examples of determination of overflow c 4 = 0 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 0 c 3 = 0 ( 9) ( 5) c 4 = 1 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 1 c 3 = 0 ( 5) ( 9) Overflow occurs only in these two cases.
70 Examples of determination of overflow c 4 = 0 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 0 c 3 = 0 ( 9) ( 5) c 4 = 1 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 1 c 3 = 0 ( 5) ( 9) Overflow = c 3 c 4 c 3 c 4
71 Examples of determination of overflow c 4 = 0 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 0 c 3 = 0 ( 9) ( 5) c 4 = 1 c 3 = 1 ( 7) ( 2) ( 7) ( 2) c 4 = 1 c 3 = 0 ( 5) ( 9) Overflow = c 3 c 4 c 3 c 4 XOR
72 Calculating overflow for 4-bit numbers with only three significant bits
73 Calculating overflow for n-bit numbers with only n-1 significant bits
74 Detecting Overflow x n 1 y n 1 x 1 y 1 x 0 y 0 c n FA c n 1 c 2 FA c 1 FA c 0 s n 1 s 1 s 0
75 Detecting Overflow (with one extra XOR) x n 1 y n 1 x 1 y 1 x 0 y 0 c n FA c n 1 c 2 FA c 1 FA c 0 s n 1 s 1 s 0 overflow
76 Another way to look at the overflow issue X= x 3 x 2 x 1 x 0 Y= y 3 y 2 y 1 y 0 S= s 3 s 2 s 1 s 0
77 Another way to look at the overflow issue X= x 3 x 2 x 1 x 0 Y= y 3 y 2 y 1 y 0 S= s 3 s 2 s 1 s 0 If both numbers that we are adding have the same sign but the sum does not, then we have an overflow.
78 Examples of determination of overflow ( 7) ( 2) ( 7) ( 2) ( 9) ( 5) ( 7) ( 2) ( 7) ( 2) ( 5) ( 9)
79 Examples of determination of overflow ( 7) ( 2) ( 7) ( 2) ( 9) ( 5) ( 7) ( 2) ( 7) ( 2) ( 5) ( 9)
80 Examples of determination of overflow x 3 = 0 y 3 = 0 s 3 = 1 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 0 s 3 = 1 ( 9) ( 5) x 3 = 0 y 3 = 1 s 3 = 0 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 1 s 3 = 0 ( 5) ( 9)
81 Examples of determination of overflow x 3 = 0 y 3 = 0 s 3 = 1 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 0 s 3 = 1 ( 9) ( 5) x 3 = 0 y 3 = 1 s 3 = 0 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 1 s 3 = 0 ( 5) ( 9) In 2's complement, both 9 and -9 are not representable with 4 bits.
82 Examples of determination of overflow x 3 = 0 y 3 = 0 s 3 = 1 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 0 s 3 = 1 ( 9) ( 5) x 3 = 0 y 3 = 1 s 3 = 0 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 1 s 3 = 0 ( 5) ( 9) Overflow occurs only in these two cases.
83 Examples of determination of overflow x 3 = 0 y 3 = 0 s 3 = 1 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 0 s 3 = 1 ( 9) ( 5) x 3 = 0 y 3 = 1 s 3 = 0 ( 7) ( 2) ( 7) ( 2) x 3 = 1 y 3 = 1 s 3 = 0 ( 5) ( 9) Overflow = x 3 y 3 s 3 x 3 y 3 s 3
84 Another way to look at the overflow issue X= x 3 x 2 x 1 x 0 Y= y 3 y 2 y 1 y 0 S= s 3 s 2 s 1 s 0 If both numbers that we are adding have the same sign but the sum does not, then we have an overflow. Overflow = x 3 y 3 s 3 x 3 y 3 s 3
85
86 How long does it take to compute all sum bits and all carry bits? x n 1 y n 1 x 1 y 1 x 0 y 0 c n FA c n 1 c 2 FA c 1 FA c 0 s n 1 s 1 s 0
87 Can we perform addition even faster? The goal is to evaluate very fast if the carry from the previous stage will be equal to 0 or 1.
88 The Full-Adder Circuit [ Figure 3.3c from the textbook ]
89 The Full-Adder Circuit Let's take a closer look at this. [ Figure 3.3c from the textbook ]
90 Decomposing the Carry Expression c i1 = x i y i x i c i y i c i
91 Decomposing the Carry Expression c i1 = x i y i x i c i y i c i c i1 = x i y i (x i y i )c i
92 Decomposing the Carry Expression c i1 = x i y i x i c i y i c i c i1 = x i y i (x i y i )c i c i y i x i c i1
93 Another Way to Draw the Full-Adder Circuit c i1 = x i y i x i c i y i c i c i1 = x i y i (x i y i )c i c i y i s i x i c i1
94 Another Way to Draw the Full-Adder Circuit c i1 = x i y i (x i y i )c i c i y i s i x i c i1
95 Another Way to Draw the Full-Adder Circuit c i1 = x i y i (x i y i )c i g i p i c i y i s i x i c i1
96 Another Way to Draw the Full-Adder Circuit g - generate p - propagate c i1 = x i y i (x i y i )c i g i p i c i y i s i x i p i g i c i1
97 Yet Another Way to Draw It (Just Rotate It) x i y i g i p i c i c i1 s i
98 Now we can Build a Ripple-Carry Adder x 1 y 1 x 0 y 0 g 1 p 1 g 0 p 0 c 2 c 1 c 0 Stage 1 Stage 0 s 1 s 0 [ Figure 3.14 from the textbook ]
99 Now we can Build a Ripple-Carry Adder x 1 y 1 x 0 y 0 g 1 p 1 g 0 p 0 c 2 c 1 c 0 Stage 1 Stage 0 s 1 s 0 [ Figure 3.14 from the textbook ]
100 The delay is 5 gates (122) x 1 y 1 x 0 y 0 g 1 p 1 g 0 p 0 c 2 c 1 c 0 Stage 1 Stage 0 s 1 s 0
101 n-bit ripple-carry adder: 2n1 gate delays x 1 y 1 x 0 y 0 g 1 p 1 g 0 p 0 c 2 c 1 c 0... Stage 1 Stage 0 s 1 s 0
102 Decomposing the Carry Expression c i1 = x i y i x i c i y i c i c i1 = x i y i (x i y i )c i g i p i c i1 = g i p i c i c i1 = g i p i (g i-1 p i-1 c i-1 ) = g i p i g i-1 p i p i-1 c i-1
103 Carry for the first two stages c 1 = g 0 p 0 c 0 c 2 = g 1 p 1 g 0 p 1 p 0 c 0
104 The first two stages of a carry-lookahead adder x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 1 s 0 [ Figure 3.15 from the textbook ]
105 It takes 3 gate delays to generate c 1 x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 1 s 0
106 It takes 3 gate delays to generate c 2 x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 1 s 0
107 The first two stages of a carry-lookahead adder x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 1 s 0
108 It takes 4 gate delays to generate s 1 x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 1 s 0
109 It takes 4 gate delays to generate s 2 x 1 y 1 x 0 y 0 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 s 2 s 1 s 0
110 N-bit Carry-Lookahead Adder It takes 3 gate delays to generate all carry signals It takes 1 more gate delay to generate all sum bits Thus, the total delay through an n-bit carry-lookahead adder is only 4 gate delays!
111 Expanding the Carry Expression c i1 = g i p i c i c 1 = g 0 p 0 c 0 c 2 = g 1 p 1 g 0 p 1 p 0 c 0 c 3 = g 2 p 2 g 1 p 2 p 1 g 0 p 2 p 1 p 0 c 0... c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0
112 Expanding the Carry Expression c i1 = g i p i c i c 1 = g 0 p 0 c 0 c 2 = g 1 p 1 g 0 p 1 p 0 c 0 c 3 = g 2 p 2 g 1 p 2 p 1 g 0 p 2 p 1 p 0 c 0... c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 Even this takes only 3 gate delays p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0
113 A hierarchical carry-lookahead adder with ripple-carry between blocks x y x y x 15 8 y 15 8 x 7 0 y 7 0 c c 32 Block 24 3 Block 2 c 16 Block 1 c 8 Block 0 c 0 s s s 15 8 s 7 0
114 A hierarchical carry-lookahead adder with ripple-carry between blocks x y x y x 15 8 y 15 8 x 7 0 y 7 0 c c 32 Block 24 3 Block 2 c 16 Block 1 c 8 Block 0 c 0 s s s 15 8 s 7 0
115 A hierarchical carry-lookahead adder with ripple-carry between blocks x y x y x 15 8 y 15 8 x 7 0 y 7 0 c 32 c 24 c 16 c 8 c 0 s s s 15 8 s 7 0
116 A hierarchical carry-lookahead adder with ripple-carry between blocks x y x 15 8 y 15 8 x 7 0 y 7 0 c 32 Block c 3 24 c 16 Block 1 c 8 Block 0 c 0 s s 15 8 s 7 0 [ Figure 3.16 from the textbook ]
117 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 s s 15 8 s 7 0 c 32 c 16 c 8 Second-level lookahead [ Figure 3.17 from the textbook ]
118 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 c 32 s s 15 8 s 7 0 c 32 c 16 c 8 Second-level lookahead
119 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 c 32 s s 15 8 s 7 0 c 32 c 16 c 8 Second-level lookahead
120 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 c 32 s s 15 8 s 7 0 c 32??? c 16 c 8 Second-level lookahead
121 The Hierarchical Carry Expression c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0
122 The Hierarchical Carry Expression c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0
123 The Hierarchical Carry Expression c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 G 0 p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0 P 0
124 The Hierarchical Carry Expression c 8 = g 7 p 7 g 6 p 7 p 6 g 5 p 7 p 6 p 5 g 4 G 0 p 7 p 6 p 5 p 4 g 3 p 7 p 6 p 5 p 4 p 3 g 2 p 7 p 6 p 5 p 4 p 3 p 2 g 1 p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0 P 0 c 8 = G 0 P 0 c 0
125 The Hierarchical Carry Expression c 8 = G 0 P 0 c 0 c 16 = G 1 P 1 c 8 = G 1 P 1 G 0 P 1 P 0 c 0 c 24 = G 2 P 2 G 1 P 2 P 1 G 0 P 2 P 1 P 0 c 0 c 32 = G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G 0 P 3 P 2 P 1 P 0 c 0
126 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 s s 15 8 s 7 0 c 32 c 16 c 8 Second-level lookahead [ Figure 3.17 from the textbook ]
127 A hierarchical carry-lookahead adder x y x 15 8 y 15 8 x 7 0 y 7 0 Block 3 c 24 Block 1 Block 0 c 0 G 3 P 3 G 1 P 1 G 0 P 0 s s 15 8 s 7 0 c 32 c 16 c 8 c 32 =G 3 P 3 G 2 P 3 P 2 G 1 P 3 P 2 P 1 G 0 P 3 P 2 P 1 P 0 c 0 Second-level lookahead c 16 = G 1 P 1 G 0 P 1 P 0 c 0 c 8 = G 0 P 0 c 0 [ Figure 3.17 from the textbook ]
128 Hierarchical CLA Adder Carry Logic Block 2 P1 P0 c0 p7 x7 y7 g7 x6 y6 p7g6 g6 p7p6g5 p7p6p5g4 Block 1 p7p6p5p4g3 p7p6p5p4p3g2 p7p6p5p4p3p2g1 p7p6p5p4p3p2p1g0 P0 c0 C8 5 gate delays C16 5 gate delays C24 5 Gate delays C32 5 Gate delays SECOND LEVEL HIERARCHY c16 G1 P1 G0 P0 c0 c8 P1 G0 G0 P1 P0 c0 Block 3 Block 2 Block 1 c 0 p 17 c 17 p 9 c 9 p 0 g 0 c 1 g 17 g 9 FIRST LEVEL HIERARCHY
129 Hierarchical CLA Critical Path Block 2 p7 x7 y7 g7 x6 y6 p7g6 g6 p7p6g5 p7p6p5g4 Block 1 p7p6p5p4g3 p7p6p5p4p3g2 p7p6p5p4p3p2g1 p7p6p5p4p3p2p1g0 G1 G0 P0 c0 c8 P1 P1 G0 G0 P1 P0 c0 c16 P1 P0 c0 P0 c0 C9 7 gate delays C17 7 gate delays C25 7 Gate delays SECOND LEVEL HIERARCHY Block 3 Block 2 Block 1 c 0 p 17 c 17 p 9 c 9 p 0 g 0 c 1 g 17 g 9 FIRST LEVEL HIERARCHY
130 Total Gate Delay Through a Hierarchical Carry-Lookahead Adder Is 8 gates 3 to generate all Gj and Pj 2 to generate c8, c16, c24, and c32 2 to generate internal carries in the blocks 1 to generate the sum bits (one extra XOR)
131 Questions?
132 THE END
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