3. Combinational Circuit Design

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1 CSEE 3827: Fundamentals of Computer Systems, Spring 2 3. Combinational Circuit Design Prof. Martha Kim (martha@cs.columbia.edu) Web:

2 Outline (H&H 2.8, 5.2) Standard combinational circuits Decoder Encoder / priority encoder (bonus, not in text) Code converter (bonus, not in text) Multiplexer Addition Half and full adders Ripple carry adder Carry lookahead adder Subtraction Comparator (!= in lecture, < in text) ALU (in text, not covering yet) Shifter 2

3 Combinational circuits Combinational circuits are stateless The outputs are functions only of the inputs Inputs Combinational circuit Outputs 3

4 Hierarchical design 3-4 Big Circuit A N MX B Design small circuits to be used in a bigger circuit A B MX N ME E A 2 B 2 MX N 2 A 3 B 3 MX N 3 Smaller Circuits (a) A i N B i MX N i N N 2 N 3 ME E (b) (c) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 4

5 Hierarchical design (It s a comparator!) 3-4 A N MX B (4-bit equality comparator) A B MX N ME E A 2 B 2 MX N 2 A 3 B 3 MX N 3 (a) A i (NEQ) N B i MX N i N N 2 N 3 ME E (b) (c) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 5

6 Enabler circuits 3-5 Output is enabled (F=A) only when input ENABLE signal is asserted (EN=) XA EN (a) F EN F A EN X A EN F (b) F A 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 6

7 Decoder-based circuits Converts n-bit input to m-bit output, where n <= m <= 2 n A B C 3:8 decoder Standard Decoder: i th output =, all others =, where i is the binary representation of the input () 7

8 Decoder-based circuits Converts n-bit input to m-bit output, where n <= m <= 2 n A B 3:8 decoder C e.g., = (i=5) Standard Decoder: i th output =, all others =, where i is the binary representation of the input () 7

9 Internal design of :2 decoder 3-7 A D D D A A D A (a) (b) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 8

10 Internal design of 2:4 decoder 3-8 A A A D D D 2 D 3 A D A A D A A (a) D 2 A A D 3 A A (b) 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 9

11 Hierarchical design of 2:4 decoder b :2 decoder 'b b 'b'a 'ba a :2 decoder 'a a b'a ba 2:4 decoder Can build 2:4 decoder out of two :2 decoders (and some additional circuitry)

12 Hierarchical design of 3:8 decoder c :2 decoder 'c c 'c'b'a 'c'ba 'b'a 'cb'a b a 2:4 decoder 'ba b'a 'cba ba c'b'a c'ba cb'a cba 3:8 decoder

13 Encoders 2 Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2 n 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e T 3-7 TABLE 3-7 Truth Table for Octal-to-Binary Encoder Inputs Outputs D 7 D 6 D 5 D 4 D 3 D 2 D D A 2 A A

14 Decoder and encoder summary n{ Decoder }2 n BCD values One-hot encoding n{ n Encoder }2 Note: for Encoders - input is assumed to have just one, the rest s 3

15 In class design: priority encoder A priority encoder takes 2^n bit input (I) and produces n bits of output (K) indicating in BCD the position of the most significant on the input. I3 I2 I I K K I Priority Encoder K x x x x x x We will leverage a regular encoder which takes 2^n bit one-hot encoded input (J) and produces n bits of output (K) indicating in BCD the position of the on the input. J3 J2 J J K K J Encoder K 4

16 In class design: priority encoder (2) This gets us part of the way there, leaving us with a simpler problem of translating I into J: I? J Encoder K I3 I2 I I J3 J2 J J x Priority Encoder x x x x x From inspection of the truth table we can see the following definitions of Jx. Could also have used k-maps. J3 = I3 J2 = I2`I3 J = I`I2`I3 J = I`I`I2`I3 NB: An input i = x is still a don t care, it means for all possible values of i. So here input xxx means any 4-bit input starting with a, i.e.,,,,,,... 5

17 General code conversion 3-3 a f b e g d c (a) Segment designation (b) Numeric designation for display 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 6

18 Code conversion Input Output a f e g d b c Va W X Y Z a b c d e f g l X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 7

19 f e Code conversion a b g c d e.g., what outputs lights up when input V=4? Input Output Va W X Y Z a b c d e f g l X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8

20 { Code conversion Input Output a f e b g c d W= For what values does output f light up for? { X X X X X X { Z= Y= { X= Va W X Y Z a b c d e f g l X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 9

21 { Algebra and Circuit for f Y= f = W + YZ + XZ + XY = W + (X+Y)Z + XY W= { X X X X X X { X= { Z= W X f Y Z 2

22 Multiplexers (or Muxes) Combinational circuit that selects binary information from one of many input lines and directs it to one output line n 2 inputs output n selection bits indicate (in binary) which input feeds to the output 2

23 Multiplexers (or Muxes) Combinational circuit that selects binary information from I2 one of many input lines and directs it to one output line I I I3 I 4 I5 I6 I7 I5 n 2 inputs output n selection bits indicate (in binary) which input feeds to the output 2

24 Internal mux organization 3-26 Selector Logic S S Decoder Enabler logic 4 2 AND-OR S Decoder S I I Y Or gate passes through the nonzeroed out Ii Y I 2 Only AND gate passes through I 3 AND gates zero out unselected Ii 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 22

25 In class exercise How would you implement an 8: mux using two 4: muxes? 23

26 Multiplexer truth table n{ 2 Mux n { 2^n inputs n-bit BCD value output a x x x x x x x a x b x x x x x x b x x c x x x x x c x x x d x x x x d x x x x e x x x e x x x x x f x x f x x x x x x g x g x x x x x x x h h 24

27 Demultiplexers (Demuxes) Demux n }2 n { input n-bit BCD value 2^n outputs a a b b c c d d e e f f g g h h 25

28 Muxes and demuxes called steering logic Mux Demux merge fork 26

29 Representing Functions with Decoders and MUXes e.g., F = AC + BC A B C minterm F A BC 3-to-8 Decoder 8-to- MUX Decoder: OR minterms for which F should evaluate to A B C MUX: Feed in the value of F for each minterm 27

30 A Slick MUX trick Can use a smaller MUX with a little trick e.g., F = AC + BC Note for rows paired below, A&B have same values, C iterates between & For the pair of rows, F either equals,, C or C A B C minterm F } } } } F = F = C F = C F = C 4-to- MUX AB AB AB AB A B 28

31 Slick MUX trick: Example 2 e.g., F = AC + BC + AC A B C minterm F } } } F = F = C F = C } F = C C 4-to- MUX AB AB AB AB A B 29

32 Addition: The Half-Adder Addition of 2 bits: A & B produces a summand (S) and carry (C) A B S C XOR gate S = A B A S C = AB B C But to do addition, we really need to add 3 bits at a time (to account for carries), e.g., carry bits + 3

33 The Full Adder Takes as input 2 digits (A&B) and a previous carry (P) P B A P A B C S S: C: P P S C B A B A S = A B P C = AB + AP + BP A B full adder C P S 3

34 5-bit ripple carry adder Computes a4a3a2aa + b4b3b2bb a4 b4 a3 b3 a2 b2 a b a b full adder full adder full adder full adder full adder C s4 s3 s2 s s Note how computation ripples through adders from left to right Each full adder s has depth 2 (inputs pass through 2 gates to reach output) Full adder that computes si cannot start its computation until previous full adder computes carry The longest depth in a k-bit ripple carry adder is 2k 32

35 Adder/subtractor for # s in 2 s complement form 4-7 B 3 A 3 B 2 A 2 B A B A S=: B S unchanged, C=: add C 4 C 3 C 2 C C FA FA FA FA S 3 S 2 S S S=: B complemented, C= (bits flipped and added): subtract 28 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 33

36 Handling overflow twos-complement (5) (3) (-8) (-5) (-3) (-8) (-6) (-3) (7) (-6) (3) (-3) 34

37 Handling overflow c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s n bit two s comp: -2^n <---> 2^n - split into pos and neg ranges and find smallest and largest possible results. show that they re in range for twos comp. a3 b3 c3 c4 s3 overflow sum of two pos is pos sum of two negs is neg 35

38 Overflow computation in adder/subtractor For 2 s complement, overflow if 2 most significant carries differ C4 FA C3 FA = then no overflow, = then overflow 36

39 Ripple-Carry adder circuit depth A3A2AA + B3B2BB = S3S2SS B3 A3 B2 A2 B A B A Depth of a circuit is the longest (most gates to go through) path Overflow has depth 8 S3 has depth 7 In general, Si has depth 2i+ in Ripple-Carry Adder Overflow S3 S2 S S 37

40 Carry lookahead adder (CLA) Goal: produce an adder of shorter circuit depth Start by rewriting the carry function ci+ = aibi + aici + bici ci+ = aibi + ci (ai+bi) ci+ = gi + ci (pi) carry generate gi = aibi carry propagate pi = ai + bi 38

41 Carry lookahead adder (CLA) (2) Can recursively define carries in terms of propagate and generate signals c = g + cp c2 = g + cp = g + (g + cp)p = g + gp + cpp c3 = g2 + c2p2 = g2 + (g + gp + cpp)p2 = g2 + gp2 + gpp2 + cppp2 ith carry has i+ product terms, the largest of which has i+ literals If AND, OR gates can take unbounded inputs: total circuit depth is 2 (SoP form) If gates take 2 inputs, total circuit depth is + log2 k for k-bit addition 39

42 Carry lookahead adder (CLA) (3) c = c = g + cp c2 = g + gp + cpp c3 = g2 + gp2 + gpp2 + cppp2 c4 = g3 + g2p3 + gp2p3 + gpp2p3 + cppp2p3 s = a b c s = a b c s2 = a2 b2 c2 s3 = a3 b3 c3 s4 = a4 b4 c4 B2 A2 B A B A g2 p2 g p g p c Depth of 3 for all ci Depth of 4 for all si, i> c3 Note: gates take only 2 inputs: depth increases by a log2 factor: still much less than linear of ripple-carry adder 4

43 Contraction Contraction is the simplification of a circuit through constant input values. 4

44 Contraction example: adder to incrementer What is the hardware and delay savings of implementing an incrementer using contraction? a4 b4 a3 b3 a2 b2 a b a b adder adder adder adder adder s4 s3 s2 s s Can be reduced to half-adders Incrementer circuit a S C S=a, C=a 42

45 Multi-wire notation Useful when running a bunch of bits in parallel to the same (similar place) O I C O... I C2 C k C2 Ok- Ik- Ok Ik k wires k k k wires 43

46 Shifter Circuit Shifts bits of a word: Ak-Ak-2...A2AA k Shifter n n selector bits k Bk-Bk-2...B2BB Various types of shifters Barrel: selector bits indicate (in binary) how far bits shift selector value = j, then Bi = Ai-j bits can wraparound Bi (mod 2 n ) = Ai-j (mod 2 n ) or rollout (Bi= for i<j) L/R with enable: n=2, high bit enables, low bit indicates direction (e.g., =left [Bi = Ai-], =right [Bi = Ai+]) 44

47 Barrel Shifter Design with wraparound (using MUXs) A3 A2 A A MUX MUX MUX MUX SS B3 B2 B B Basic form of design: Each Ai feeds into each MUX connecting to Bj into input (j-i) mod 4 45

48 Barrel Shifter Design with wraparound (using MUXs) A3 A2 A A MUX MUX MUX MUX 2 B3 B2 B B Basic form of design: Each Ai feeds into each MUX connecting to Bj into input (j-i) mod 4 Selector is (i.e., 2 binary): each MUX entry 2 is selected A flows into the 2 input of the MUX whose output is B2 46

49 Barrel Shifter Design with wraparound (using MUXs) A3 A2 A A MUX MUX MUX MUX 2 B3 B2 B B Basic form of design: Each Ai feeds into each MUX connecting to Bj into input (j-i) mod 4 Selector is (i.e., 2 binary): each MUX entry 2 is selected B3 B2 B B=A A A3 A2 47

50 L/R Shift w/ Rollout A3 A2 A A MUX MUX MUX MUX SS B3 B2 B B Basic form of design: & MUX selectors (S = ) feed Ai to Bi 2 MUX selector feeds from left (Bi = Ai-), 3 MUX from right (Bi = Ai+) Note feeds ( s roll in when bits rollout) 48

51 L/R Shift w/ Rollout A3 A2 A A MUX MUX MUX MUX B3 B2 B B Basic form of design: & MUX selectors (S = ) feed Ai to Bi 2 MUX selector feeds from left (Bi = Ai-), 3 MUX from right (Bi = Ai+) Note feeds ( s roll in when bits rollout) 49

CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits

CSEE 3827: Fundamentals of Computer Systems Combinational Circuits Outline (M&K 3., 3.3, 3.6-3.9, 4.-4.2, 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder