14:332:231 DIGITAL LOGIC DESIGN

Transcription

1 4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Lecture #4: Adders, ubtracters, and ALUs Vector Binary Adder [Wakerly 4 th Ed., ec. 6., p. 474] ingle bit Improved adder Binary addition is used frequently Addition Development: Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance (check in Wikipedia: 2of 24

2 Functional Block: Half Adder A 2-input, -bit width binary adder that performs the following computations: CO H A half adder adds two bits to produce a two-bit sum The low-order bit is named half sum (H), and the high-order bit is named carry out (CO) The half adder can be specified as a truth table for H and CO CO H 3of 24 Half Adder Half-adder for -bit addends CO H H CO half sum: H = H carry out: CO = CO 4of 24 2

3 Full Adder [Recall Binary Addition from Lecture #2] Basic building block is full adder -bit-wide adder, produces sum and carry outputs Truth table: Ci + Co Row Inputs Outputs Cout 5of 24 Full Adder from Half Adders -bit half adder A H B CO -bit full adder C i i Ai H Bi Ci 6of 24 3

4 Full Adder first term = H CIN = CIN = ( + ) CIN = CIN + CIN + CIN + CIN first term direct first term complement COUT = + CIN + CIN carry generated internally carry generated by CIN 7of 24 Logic Optimization: Full Adder Full adder Karnaugh map Inputs Outputs : Row Cout Cout: = Cout = of 24 4

5 Full Adder Circuit a) Gate-level circuit diagram b) Logic symbol c) Alternate logic symbol suitable for cascading a) CIN COUT b) c) full adder CIN COUT COUT CIN 9of 24 ubtraction ubtraction is the same as addition of the twos complement Recall Lecture #2: The two s complement is the bit-by-bit complement plus Therefore, = + + Complement inputs to adder, set first C in to of 24 5

6 ubtractor Design Using Adders Ripple subtractor i 74x4 i C 3 C 2 C C 4 COUT CIN COUT CIN COUT CIN COUT CIN 3 2 of 24 ubtractor Design Using Adders Ripple subtractor x n y n x n 2 y n 2 x y b_l n b_l n BOUT BIN D BOUT D BIN b_l n 2... b_l BOUT D b_l BIN d n d n 2 d 2 of 24 6

7 2 s Complement Adder/ubtractor ubtraction can be done by addition of the 2 s Complement.. Complement each bit ( s Complement.) 2. Add to the result. The circuit shown computes both A + B and A B: For =, subtract, the 2 s complement of B is formed by using ORs to form the s comp and adding the applied to C. For =, add, B is passed through unchanged 3 of 24 How to Detect Overflow Rule was: ign of the two operands identical and different from the sign of the result [recall Lecture #3] ign = most significant bit (MB) OVR = n n n + n n n or: OVR = C n C n carry-in different from carry-out OVR = + = OVR = = 2 n or 4 of 24 7

8 Ripple Adder To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:) and B(3:) to get a sum vector (3:) Note: carry-out of block i becomes carry-in of block i + Description Carry in Augend Addend um Carry out Bit index 3 2 Name Ci Ai Bi i C i+ 5 of 24 Ripple Adder C 3 C 2 C C 4 COUT CIN COUT CIN COUT CIN COUT CIN C 3 2 It is relatively slow: For n bits, the worst case is: All of the adder s bits (and c ) are present simultaneously tadd = t C OUT + (n 2) t CINCOUT + t CIN LB (out C ) MB (in C n ) Carry look-ahead adders are the solution + 6 of 24 8

9 Carry Lookahead Adder Uses a different circuit to calculate the carry out (calculates it ahead of the addition), to speed up the overall addition Requires more complex circuits Trade-off: speed vs. area (complexity, cost) 7 of 24 Carry Look-Ahead Addition Carry generate: input bits combination (x i,y i ) that produces a carry-out of (c i+ = ) independent of lowerorder bits (x x i, y y i ) and c. Carry propagate: input bits combination (x i,y i ) that produces a carry-out of (c i+ = ) when c i =. Inputs Outputs Cout c i c i+ No carry No carry No carry Carry propagated No carry Carry propagated Carry generated Carry generated & propagated x i y i g i = x i y i p i = x i + y i c i+ = g i + p i c i carry-generate carry-propagate p i g i Note that we could use half adder: pi = xi yi 8 of 24 9

10 4-bit Carry Lookahead Adder Conceptual diagram x3 y3 p3 g3 c3 s3 p i see previous slide x2 y2 p2 g2 c2 s2 s i = H i c i = p i c i c i+ = g i + p i c i x y p g c s Note that g i = p i = (but not vice versa) g i p i g i x y p g c s 9 of 24 Carry Lookahead Logic tructure of one stage of a carry-lookahead adder: g i = x i y i p i = x i + y i carry-generate signal carry-propagate signal x i y i x i hs i c i s i x y i Carry Lookahead Logic y c 2 of 24

11 Carry equations for first 4 adder stages c = p (g + c ) c 2 = p (g + c ) = p (g + p (g + c )) = p (g + p ) (g + g + c ) distributivity theorem c 3 = p 2 (g 2 + c 2 ) = p 2 (g 2 + p (g + p ) ( g + g + c )) = p 2 (g 2 + p ) (g 2 + g + p ) (g 2 + g + g + c ) c 4 = p 3 (g 3 + c 3 ) = p 3 (g 3 + p 2 (g 2 + p ) (g 2 + g + p ) (g 2 + g + g + c )) = p 3 (g 3 + p 2 ) (g 3 + g 2 + p ) (g 3 + g 2 + g + p ) (g 3 + g 2 + g + g + c ) 2 of 24 74x283 4-bit Adder Uses carry lookahead (CLA) internally Differences from general CLA design: Active-low versions of carry-generate (g i ) and carry-propagate (p i ) (b/c inverting gates are faster) Algebraic manipulation of the half-sum: hs i = x i y i = x i y i + x i y i = (x i + y i ) (x i + y i ) = (x i + y i ) ( x i y i ) = p i g i Creates the carry signals using INVERT-OR- AND (has delay as a single inverting gate): ci+ = p i g i + p i c i = p i (g i + c i ) ee Wakerly 4 th ed., page 48, for carry equations 74x C A B A B A2 B2 A3 B C4 22 of 24

12 74x283 4-bit Adder (detail) p (g + p ) (g + g + c ) p (g + c ) generate g p half sum hs c c propagate carry-in from previous stage 23 of 24 6-bit Group-ripple Adder Ripple carry between groups Total propagation delay 8 inverting gates 24 of 24 2