CS 140 Lecture 14 Standard Combinational Modules

Transcription

1 CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1

2 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier Adders 1. Representation of numbers 2. Full Adder 3. Half Adder 4. Ripple-Carry Adder 5. Carry Look Ahead Adder 6. Prefix Adder 7. Carry Save Adder ALU Multiplier Division 2

3 Operators Specification: Data Representations Arithmetic: Algorithms Logic: Synthesis Layout: Placement and Routing 3

4 1. Representation 2 s Complement -x: 2 n -x 1 s Complement -x: 2 n -x-1 4

5 1. Representation 2 s Complement -x: 2 n -x e.g. 16-x 1 s Complement -x: 2 n -x-1 e.g. 16-x-1 Id 2 s comp. 1 s comp

6 1. Representation Id -Binary sign mag 2 s comp 1 s comp

7 Representation 1 s Complement For a negative number, we take the positive number and complement every bit. 2 s Complement For a negative number, we do 1s complement and plus one. (b n-1, b n-2,, b ): -b n-1 2 n-1 + sum i<n-1 b i 2 i 7

8 Representation 2 s Complement x+y x-y: x+2 n -y= 2 n +x-y -x+y: 2 n -x+y -x-y: 2 n -x+2 n -y = 2 n +2 n -x-y -(-x)=2 n -(2 n -x)=x 1 s Complement x+y x-y: x+2 n -y-1= 2 n -1+x-y -x+y: 2 n -x-1+y=2 n -1-x+y -x-y: 2 n -x-1+2 n -y-1 = 2 n -1+2 n -x-y-1 -(-x)=2 n -(2 n -x-1) -1=x 8

9 Examples = = -1 (2 s) = -1 (1 s) = -5 (2 s) = -5 (1 s) Check for overflow (2 s) = C4C = C4C3 9

10 Addition: 2 s Complement Overflow In 2 s complement: overflow = c n xor c n-1 Exercise: 1.Demonstrate the overflow with more examples. 2.Prove the condition. 1

11 Addition and Subtraction using 2 s Complement a b b C4 C3 overflow MUX minus Adder C in C out Sum 11

12 1-Bit Adders Half Adder Full Adder A B A B C out + C out + C in S S A B C out 1 S = A B C out = AB S 1 1 C in A B C out S S = A B C in C out = AB + AC in + BC in 12

13 Half Adder a b S um = ab + a b = a + b HA C out = ab Cout a b S um C out S um a b C out S um 13

14 Full Adder Composed of Half Adders a b HA c out sum x OR c out y z c in HA c out sum sum 14

15 Full Adder Composed of Half Adders a b c in HA c out sum y x HA c out sum z c out sum Id a b c in x y z c out s um Id x z c out

16 Adder Several types of carry propagate adders (CPAs) are: Ripple-carry adders (slow) Carry-lookahead adders (fast) Prefix adders (faster) Carry-lookahead and prefix adders are faster for large adders but require more hardware. Symbol A B C out + S C in 16

17 Ripple-Carry Adder Chain 1-bit adders together Carry ripples through entire chain Disadvantage: slow A 31 B 31 A 3 B 3 A 1 B 1 A B C out + C 31 + C 3 C 2 + C1 + C in S 31 S 3 S 1 S 17

18 Ripple-Carry Adder Delay The delay of an -bit ripple-carry adder is: t ripple = t FA where t FA is the delay of a full adder 18

19 Carry-Lookahead Adder Compress the logic levels of C out Some definitions: Generate (G i ) and propagate (P i ) signals for each column: A column will generate a carry out if A i AD B i are both 1. G i = A i B i A column will propagate a carry in to the carry out if A i OR B i is 1. P i = A i + B i The carry out of a column (C i ) is: C i+1 = A i B i + (A i + B i )C i = G i + P i C i 19

20 Carry Look Ahead Adder C 1 = a b + (a +b )c = g + p c C 2 = a 1 b 1 + (a 1 +b 1 )c 1 = g 1 + p 1 c 1 = g 1 + p 1 g + p 1 p c C 3 = a 2 b 2 + (a 2 +b 2 )c 2 = g 2 + p 2 c 2 = g 2 + p 2 g 1 + p 2 p 1 g + p 2 p 1 p c C 4 = a 3 b 3 + (a 3 +b 3 )c 3 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g + p 3 p 2 p 1 p c q i = a i b i p i = a i + b i a 3 b 3 a 2 b 2 a 1 b 1 a b g 3 p 3 g 2 p 2 g 1 p 1 g p c c 4 c 3 c 2 c 1 2

21 Carry-Lookahead Addition Step 1: compute generate (G) and propagate (P) signals for columns (single bits) Step 2: compute G and P for k-bit blocks Step 3: C in propagates through each k-bit propagate/generate block 21

22 32-bit CLA with 4-bit blocks B 31:28 A 31:28 B 27:24 A 27:24 B 7:4 A 7:4 B 3: A 3: C out 4-bit CLA Block C 28 4-bit CLA Block C 24 C 8 4-bit CLA Block C 4 4-bit CLA Block C in S 31:28 S 27:24 S 7:4 S 3: B 3 A 3 B 2 A 2 B 1 A 1 B A + C 3 + C 2 + C 1 + C in S 3 S 2 S 1 S G 3: G 3 P 3 G 2 P 2 G 1 P 1 G C out C in P 3: P 3 P 2 P 1 P 22

23 Delay of an -bit carry-lookahead adder with k-bit blocks: t CLA = t pg + t pg_block + (/k 1)t AD_OR + kt FA where Carry-Lookahead Adder Delay t pg : delay of the column generate and propagate gates t pg_block : delay of the block generate and propagate gates t AD_OR : delay from C in to C out of the final AD/OR gate in the k-bit CLA block An -bit carry-lookahead adder is generally much faster than a ripple-carry adder for > 16 23

24 Prefix Adder Computes the carry in (C i-1 ) for each of the columns as fast as possible and then computes the sum: S i = (A i B i ) C i Computes G and P for 1-bit, then 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the carry in (generate signal) is known for each column Has log 2 stages 24

25 Prefix Adder A carry in is produced by being either generated in a column or propagated from a previous column. Define column -1 to hold C in, so G -1 = C in, P -1 = Then, the carry in to col. i = the carry out of col. i-1: C i-1 = G i-1:-1 G i-1:-1 is the generate signal spanning columns i-1 to -1. There will be a carry out of column i-1 (C i-1 ) if the block spanning columns i-1 through -1 generates a carry. Thus, we rewrite the sum equation:s i = (A i B i ) G i-1:-1 Goal: Compute G :-1, G 1:-1, G 2:-1, G 3:-1, G 4:-1, G 5:-1, (These are called the prefixes) 25

26 Prefix Adder The generate and propagate signals for a block spanning bits i:j are: G i:j = G i:k + P i:k G k-1:j P i:j = P i:k P k-1:j In words, these prefixes describe that: A block will generate a carry if the upper part (i:k) generates a carry or if the upper part propagates a carry generated in the lower part (k-1:j) A block will propagate a carry if both the upper and lower parts propagate the carry. 26

27 Prefix Adder Schematic :13 12:11 1:9 8:7 6:5 4:3 2:1 :-1 14:11 13:11 1:7 9:7 6:3 5:3 2:-1 1:-1 14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1 14:-1 13:-1 12:-1 11:-1 1:-1 9:-1 8:-1 7: Legend i i:j i A i B i P i:k P k-1:j G i:k G k-1:j G i-1:-1 A i B i P i:i G i:i P i:j G i:j 27 S i

28 Carry Save Adder Fast and low power addition for multiple additions A Redundant umber System Save the Partial Solution for Multiple Additions One Bit Propagation for Each Addition 28

29 Carry Save Adder: A Redundant umber System For each digit, we have two bits (,) (,1) (1,) (1,1) Weight (,) Weight 1 (,1) (1,) Weight 2 (1,1) 29

30 Carry Save Adder: A Simple Example Weight n1 1 1 n n n

31 Carry Save Adder: A Simple Example Weight n n n n n n A=n1+n n B=A+n n C=B+n Sum

32 Carry Save Adder: One Digit Logic Diagram Addend in two bit Addend in one bit A B Full Adder Cin Full Adder Cout Sum Carry out form digit i-1 Carry out to digit i+1 Sum in two bits For digit i, the addition of addend in two bits and addend in one bit produces the carry out and sum. The sum and the carry out from digit i-1 become the two bit output at digit i. 32

33 Carry Save Adder: Three Digit Logic Diagram Addend in two bit Addend in two bit Addend in two bit Addend in one bit Addend in one bit Addend in one bit A B Full Adder A B Full Adder A B Full Adder Full Full Full Cin Cout Adder Cin Adder Cin Cout Adder Cout Sum Sum Sum Cout to digit i+2 Cout to digit i+1 Cout form digit i-1 Cout form digit i-2 Sum in two bits Sum in two bits Sum in two bits For digit i, the addition of addend in two bits and addend in one bit produces the carry out and sum. The sum and the carry out from digit i-1 become the two bit output at digit i. 33

34 Carry Save Adder Procedure of carry save addition system 1. Convert the first addend to the redundant number system 2. For intermediate solution, perform carry save addition. 3. Split the redundant number into two numbers. 4. Perform the addition on the two numbers to general the solution. 34

35 The delay of an -bit prefix adder is: t PA = t pg + log 2 (t pg_prefix ) + t XOR where Prefix Adder Delay t pg is the delay of the column generate and propagate gates (AD or OR gate) t pg_prefix is the delay of the black prefix cell (AD-OR gate) 35

36 Adder Delay Comparisons Compare the delay of 32-bit ripple-carry, carrylookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is 1 ps and the full adder delay is 3 ps. 36

37 Adder Delay Comparisons Compare the delay of 32-bit ripple-carry, carrylookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is 1 ps and the full adder delay is 3 ps. t ripple = t FA = 32(3 ps) = 9.6 ns t CLA = t pg + t pg_block + (/k 1)t AD_OR + kt FA = [ (7)2 + 4(3)] ps = 3.3 ns t PA = t pg + log 2 (t pg_prefix ) + t XOR = [1 + log 2 32(2) + 1] ps = 1.2 ns 37

38 Comparator: Equality Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A 1 Equal Equal B 1 A B 38

39 Comparator: Less Than For unsigned numbers A B - [-1] A < B 39

40 Arithmetic Logic Unit (ALU) F 2: Function A ALU Y B 3 F A & B 1 A B 1 A + B 11 not used 1 A & ~B 11 A ~B 11 A - B 111 SLT 4

41 ALU Design A B F 2: Function A & B 1 1 A B F 2 1 A + B C out + [-1] S 11 not used 1 A & ~B Zero Extend 3 2 Y 1 2 F 1: 11 A ~B 11 A - B 111 SLT 41

42 Set Less Than (SLT) Example A 1 B Configure a 32-bit ALU for the set if less than (SLT) operation. Suppose A = 25 and B = 32. F 2 C out + [-1] S Zero Extend F 1: Y 42

43 Set Less Than (SLT) Example C out Zero Extend 3 A 1 + [-1] S 2 Y B 1 2 F 2 F 1: Configure a 32-bit ALU for the set if less than (SLT) operation. Suppose A = 25 and B = 32. A is less than B, so we expect Y to be the 32-bit representation of 1 (x1). For SLT, F 2: = 111. F 2 = 1 configures the adder unit as a subtracter. So = -7. The two s complement representation of -7 has a 1 in the most significant bit, so S 31 = 1. With F 1: = 11, the final multiplexer selects Y = S 31 (zero extended) = x1. 43

44 Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: 111 >> 2 = 11 Ex: 111 << 2 = 1 Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb). Ex: 111 >>> 2 = 1111 Ex: 111 <<< 2 = 1 Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: 111 ROR 2 = 111 Ex: 111 ROL 2 =

45 Shifter Design A 3 A 2 A 1 A shamt 1: 2 S 1: 1 1 Y 3 11 shamt 1: S 1: Y A 3: >> Y 3: 1 S 1: 1 Y S 1: 1 Y 11 45

46 Shifter x n x n-1 x x -1 s d s / n l / r En y i = x i-1 if En = 1, s = 1, and d = L = x i+1 if En = 1, s = 1, and d = R = x i if En = 1, s = = if En = yn-1 y x i+1 x i x i-1 Can be implemented with a mux s d En yi

47 Barrel Shifter shift x s O or 1 shift s 1 O or 2 shift s 2 O or 4 shift y

48 Shifters as Multipliers and Dividers A left shift by bits multiplies a number by 2 Ex: 1 << 2 = 1 (1 2 2 = 4) Ex: 1111 << 2 = 11 ( = -12) The arithmetic right shift by divides a number by 2 Ex: 1 >>> 2 = 1 (8 2 2 = 2) Ex: 1 >>> 2 = 111 ( = -4) 48

49 Multipliers Steps of multiplication for both decimal and binary numbers: Partial products are formed by multiplying a single digit of the multiplier with the entire multiplicand Shifted partial products are summed to form the result Decimal 23 x multiplicand multiplier partial products result + Binary 11 x x 42 = x 7 = 35 49

50 4 x 4 Multiplier A 3 A 2 A 1 A B B 1 A B 4 x P 8 4 A 3 A 2 A 1 A x B 3 B 2 B 1 B A 3 B A 2 B A 1 B A B A 3 B 1 A 2 B 1 A 1 B 1 A B 1 A 3 B 2 A 2 B 2 A 1 B 2 A B 2 + A 3 B 3 A 2 B 3 A 1 B 3 A B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P B 2 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 5

51 Division Algorithm Q = A/B R: remainder D: difference R = A for i = -1 to D = R - B if D < then Q i =, R = R // R < B else Q i = 1, R = D // R B R = 2R 51

52 4 x 4 Divider 52