COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHIC-LOGIC UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ

Transcription

1 OMUTERS ORGANIZATION 2ND YEAR OMUTE SIENE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHI-LOGI UNIT JOSÉ GARÍA RODRÍGUEZ JOSÉ ANTONIO SERRA ÉREZ Tema 3. La Unidad entral de roceso. A.L.U.

2 Arithmetic Logic Unit ALU Introduction Logic Operations Addition and subtraction arry propagated adder (A) Adder-Subtractor circuit Overflow arry Look-ahead Adder (LA) Multiplication Binary multiplication without sign Binary multiplication with sign Booth Algorithm Division onclusions Tema 3. La Unidad entral de roceso. A.L.U. 2

3 Introduction Introduction B A TEM D E ALU Z O Arithmetic and logic operator (one or more) Accumulator One or more temporal registers Result flags arry () Negative (N) Overflow (O or V) Zero (Z) Tema 3. La Unidad entral de roceso. A.L.U. 3

4 Logic operations Logic Operations Easy to implement Direct correspondence with the Hardware. Logic gates AND, OR, XOR, INVERTER,... Operation A B 00 0 Result 0 Tema 3. La Unidad entral de roceso. A.L.U. 4

5 Addition and subtraction Half-adder Binary half-adder (H.A.) Inputs Outputs X Y S S = X Y + X Y = X Y = X Y H.A. A S A B H.A. B S Tema 3. La Unidad entral de roceso. A.L.U. 5

6 Full Adder (F.A.) Addition and Subtraction A B F.A. Inputs Outputs in A B in S out S out S = A B in + A B in + A B in + A B in out = A B + A in + B in S = out = ( A B) in AB + in ( A B) Tema 3. La Unidad entral de roceso. A.L.U. 6

7 Full Adder (F.A.) Addition and Subtraction Usign half-adders (H.A.) H.A. A S F.A. H.A. S S B out in Tema 3. La Unidad entral de roceso. A.L.U. 7

8 Full Adder (F.A.) Addition and Subtraction Usign gates Tema 3. La Unidad entral de roceso. A.L.U. 8

9 arry ropagated Adder Addition and Subtraction To add two numbers of n bits, n full adder should be placed one after another. arry is propagated from one stage to the next one: arry ropagated Adder. B 3 A 3 B 2 A 2 B A B 0 A S 3 S 2 S S 0 Tema 3. La Unidad entral de roceso. A.L.U. 9

10 arry ropagated Adder Addition and Subtraction Adders built with logic gates using the expression: S = A B in + A B in + A B in + A B in out = A B + A in + B in B 3 A 3 B 2 A 2 B A B 0 A 0 4 8T 9T 2 6T 7T 2 4T 5T 2T 3T 0 S 3 S 2 S S 0 Tema 3. La Unidad entral de roceso. A.L.U. 0

11 arry ropagated Adder Addition and Subtraction Full adders built with half-adders A B in S out B 3 A 3 B 2 A 2 B A B 0 A 0 4 9T 8T 2 7T 6T 2 5T 4T 3T 2T 0 S 3 S 2 S S 0 Total _ Time = ( 2 n + )T Tema 3. La Unidad entral de roceso. A.L.U.

12 Subtractor circuit Addition and Subtraction The circuit works with numbers in two s complement notation. A - B = A + ((B) + ) B 3 A 3 B 2 A 2 B A B 0 A = 4 S 3 S 2 S S 0 Tema 3. La Unidad entral de roceso. A.L.U. 2

13 Adder-Subtractor ircuit Addition and Subtraction S/A B i input Total _ Time = 2( n + )T B 3 A 3 B 2 A 2 B A B 0 A 0 R/S S 3 S 2 S S 0 Tema 3. La Unidad entral de roceso. A.L.U. 3

14 Overflow detection Addition and Subtraction Two s complement Adder-Substractor with overflow detection B 3 A 3 B 2 A 2 B A B 0 A 0 R/S S 3 S 2 S S 0 V Tema 3. La Unidad entral de roceso. A.L.U. 4

15 Overflow Detection Addition and Subtraction. ase Addition of two positive numbers S OV 2. ase Addition of two negative numbers S OV Tema 3. La Unidad entral de roceso. A.L.U. 5

16 arry Look-ahead Adder Assume A and B to be 4 bits numbers arry generating signal: arry propagating signal: Addition and Subtraction i i i b a G = = = + i i i b a Tema 3. La Unidad entral de roceso. A.L.U. 6 arry on stage i: haracterized for A and B: = + i i i b a i i i i G + = G G G G + = + = + = + =

17 arry Look-ahead Adder Expanding the expressions depending on -: Addition and Subtraction G G G G G G = + + = + = Tema 3. La Unidad entral de roceso. A.L.U. 7 arries depend on ai and bi. These expressions are resolved as addition of products. Three leves of logic gates are needed to get each carry G G G G G G G = =

18 arry Look-ahead Adder Addition and Subtraction a 3 b 3 a 2 b 2 a b a 0 b 0 g 3 p 3 S 3 c 2 g 2 p 2 S 2 c g p S c 0 g 0 p 0 S 0 c - c 3 Look-ahead arry Generator Tema 3. La Unidad entral de roceso. A.L.U. 8

19 arry Look-ahead Adder Addition and Subtraction a 3 b 3 3T c 2 a 2 b 2 3T c a b 3T c 0 a 0 b 0 c - p 3 4T g 2 p 2 4T g p 4T g 0 p 0 4T T T S 3 T T S T T 2 S T T S 0 g 3 c 3 Look-ahead arry Generator 3T F.A. a i b i i- H.A. 3T H.A. T 4T S i c i Adders built with half-adders Tema 3. La Unidad entral de roceso. A.L.U. 9

20 Example (8 bits LA) Addition and Subtraction a 7 b 7 a 6 b 6 a 5 b 5 a 4 b 4 a 3 b 3 a 2 b 2 a b a 0 b 0 c 6 c 5 c 4 c 3 c 2 c c 0 c - g 7 p 7S7 g 6 p g 6 5p 5S5 g 4 p 4S4 S 6 g 3 p 3S3 g 2 p g 2 p S g 0 p 0S0 S 2 c 7 Look-ahead carry generator Look-ahead carry generator alculate the delay in this LA supposing that the adders are built with half-adders. ompare the result against a 8 bits A. Tema 3. La Unidad entral de roceso. A.L.U. 20

21 Example ( 4 bits LA) Addition and Subtraction Tema 3. La Unidad entral de roceso. A.L.U. 2

22 Example (4 bits LA) Addition and Subtraction Tema 3. La Unidad entral de roceso. A.L.U. 22

23 Multiplication Multiplication Sums and shifts algorithm If multiplicand has n bits and multiplier has m bits, them the product will have n+m bits. Binary multiplication: simple as you only multiply by or by 0. Multiplicand Multiplier roduct Tema 3. La Unidad entral de roceso. A.L.U. 23

24 Binary multipication without sign Multiplication Repeat n times If bit 0 of multiplier= then End if End repeat Sum the multiplicand to the left half of the product and place the result int the left half of the product Shift the product register bit to the right Shift the multiplier register bit to the right reliminary Version ALU Multiplicand n bits Multiplier n bits Sum Right shift Right shift roduct 2n bits Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 24

25 Binary multiplication without sign Multiplication Multiplicand 0 Multiplier roduct reliminary Version ALU Multiplicand n bits Multiplier n bits Sum Right shift Right shift roduct 2n bits Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 25

26 Binary multiplication without sign Multiplication Repeat n times If bit 0 of product register= then End if End repeat Sum the multiplicand to the left half of the product and place the result in the left half of the product. Shift the product register bit to the right Final Version Multiplicand n bits ALU Sum Right shift roduct 2n bits Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 26

27 Binary multiplication without sign Multiplication 0 0 Multiplicand 0(d Iteration 0 Initial values ALU Sum Right shift roduct Multiplier 5(d Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 27

28 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration roduct + Multiplicand ALU Sum Right shift roduct Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 28

29 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration Right shift ALU Sum Right shift roduct Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 29

30 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration 2 Right shift ALU Sum Right shift roduct Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 30

31 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration 3 roduct + Multiplicand ALU Sum Right shift roduct Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 3

32 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration 3 Right shift ALU Sum Right shift roduct Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 32

33 Binary multiplication without sign Multiplication 0 0 Multiplicand Iteration 4 Right shift ALU Sum Right shift roduct 50(d Multiplier Write ontrol Tema 3. La Unidad entral de roceso. A.L.U. 33

34 Binary multiplication without sign Multiplication Multiplicand = 00 Multiplier = 00 roduct Multiplicand Action Iteration Initial values Sum prod. and multiplicand Right shift prod. bit Right shift prod. bit Sum prod. and multiplicand Right shift prod. bit Right shift prod. bit 4 Tema 3. La Unidad entral de roceso. A.L.U. 34

35 Fast multiplication Multiplication Tema 3. La Unidad entral de roceso. A.L.U. 35

36 Binary multiplication with sign Multiplication Assume two s complement numbers A = 00 y B = 00 Apply sums and shifts algorithm 0 0 x x Wrong version Right version Tema 3. La Unidad entral de roceso. A.L.U. 36

37 Booth Algorithm Multiplication Assume Multiplicand = 2 and Multiplier = 7 (binaries 000 x 0) Booth expressed 7 = 8 - and replaced the multiplier by this decomposition: 0 = = Multiplicand x Multiplier according to A. Booth 0 Multiplicand subtraction shifts (2 zeros in the multiplier) Multiplicand addition Tema 3. La Unidad entral de roceso. A.L.U. 37

38 Booth Algorithm Multiplication urrent Bit Bit on the left Replacement (no transition) 0 - (transition to negative) 0 + (transition to positive) 0 (no transition) Example: Multiplicand = 00 y Multiplier = 000 Multiplier according to Booth = x Tema 3. La Unidad entral de roceso. A.L.U. 38

39 Booth Algorithm Multiplication q - =0 Repeat n times If q 0 = and q - = 0 then roduct h = product h - Multiplicand If q 0 = 0 and q - = then roduct h = roduct h + Multiplicand Arithmetic shift to the right of roduct and q - End repeat. Multiplicand n bits ALU Sum/Subt. Right shift roduct Multiplier q 0 q - ontrol 2n bits Tema 3. La Unidad entral de roceso. A.L.U. 39

40 Booth Algorithm Multiplication Multiplicand = 00 Multiplier = 0 Multiplicand roduct q - Action Itertion Initial values No operation Right shift Subtraction Right shift No operation Right shift No operation Right shift 4 Tema 3. La Unidad entral de roceso. A.L.U. 40

41 Division Division Division can be expressed as: Dividend = Quotient x Divisor + Remainder The remainder is smaller than the divisor. Double of space should be reserved for the dividend. Assume positive operands. Dividend Divisor Quotient Remainder Tema 3. La Unidad entral de roceso. A.L.U. 4

42 Algorithm with restoration Division Repeat n times Shift dividend to the left Dividend h = Dividend h - Divisor If Dividend h < 0 then (does not fit) else end if end repeat q 0 =0 Dividend h = Dividend h + Divisor (restore) q 0 = Divisor n bits ALU Sum/Subt. Left shift Dividend Quotient Remainder 2n bits q 0 ontrol Tema 3. La Unidad entral de roceso. A.L.U. 42

43 Algorithm with restoration Division Dividend Divisor Action Iteration Initial values _ 00 Shift bit to the left 000 0_ 00 Restar Dividend h > 0 q 0 = 000 _ 00 Shift bit to the left _ 00 Dividend h - Divisor (Subtract) Dividend h > 0 q 0 = 2 00 _ 00 Shift bit to the left 3 _ 00 Dividend h - Divisor (Subtract) Dividend h <= 0 q 0 = Dividend h + Divisor (Restore) 3 0 0_ 00 Shift bit to the left _ 00 Dividend h - Divisor (Subtract) Dividend h > 0 q 0 = 4 Rem. Quot. Tema 3. La Unidad entral de roceso. A.L.U. 43

44 Algorithm without restoration Division Dividend h = Dividend h - Divisor Repeat n times If Dividend h < 0 then Shift the Dividend to the left Dividend h = Dividend h + Divisor Else End if Shift the Dividend to the left Dividend h = Dividend h - Divisor If Dividend h < 0 then Else End if End repeat q 0 =0 q 0 = Divisor n bits Sum/Subt. ALU Left shift Dividend Quotient Remainder 2n bits ontrol Tema 3. La Unidad entral de roceso. A.L.U. 44 q 0

45 Algorithm without restoration Division Dividend Divisor Action Iteration Initial values Dividend h - Divisor 0 00 _ 000 Dividend h < 0 Shift left 0 _ 000 Dividend h + Divisor Dividend h < 0 q 0 = 0 0 0_ 000 Dividend h < 0 Shift left 2 0_ 000 Dividend h + Divisor Dividend h < 0 q 0 = _ 000 Dividend h < 0 Shift left _ 000 Dividend h + Divisor Dividend h >= 0 q 0 = _ 000 Dividend h > 0 Shift left _ 000 Dividend h - Divisor Dividend h > 0 q 0 = 4 Remain. Quotient Tema 3. La Unidad entral de roceso. A.L.U. 45

46 onclusions onclusions Adders Temporal problems with arry ropagated Adder, specially if n high. arry Look-ahead Adders improve response time of the adders. Multiplication roblems with the multiplication of signed numbers. Booth algorithm allows to multiply two s complement numbers and sometimes it reduces the number of operations if there is s or 0 s chains in the multiplier. Division Algorithm with restoration for positive numbers. For negative numbers, the sign must be preprocessed. The result s sign will depend on that. Tema 3. La Unidad entral de roceso. A.L.U. 46