Unit 16 Problem Solutions

Transcription

1 5.28 (contd) I. None II. (4, 7)ü (6, 7)ü (2, 4)ü (2, 6)ü Assignment: S =, =, =, =, = A B S Present ate Next ate W = Output S S S Present ate Next ate W = Output T input equations derived from the transition table using arnaugh maps: T A = ; T B = WA; T = WB AB; = WAB 5.29 By inspecting incoming arrows, we get: = = Y Y = = Y Y S 3 2 = = Y Y 3 = = Y Y S = Y P = Y Y Y Y S Y S Y Y Y S Y P 5.3 By inspecting incoming arrows, we get: = = Y Y Y = = Y Y Y = 2 = Y Y Y Y = Y Y Y = Y Y Unit 6 Problem Solutions See Lab Solutions in this manual. 6.5 See FL p. 662 for solution. 6.6 See FL p. 662 for solution. 6.7 (a) The state meanings are given in the following table: Name S Meaning No s have occurred One has occurred (an odd number < 2) Two s or an even number of s > 2 have occurred An odd number of s > 2 has occurred. S 3

2 6.7 (b) ate Next ate = = S S I: (, 3) II: (, ) (, 2) (2, 3) x i a i b i a i = x i a i x i a i x a i i x i a i a i = x i a i x i a i a i b i a i S ate a i b i = = a i b i S x i a i b i b i = b i x i a i x i a i bi a b i i b i b i = b i x i a i z = a n b n Note: Solution on FL p. 622 uses state assignment S =, =, =, =. 6.7 (c) Since no s have occurred, a and b are the same as S or, a = ; b = ; a i = x a x a = x ; b first cell i = b x a = } 6.7 (d) x x x 2 x n a b ell a 2 a 3 b2 ell 2 b3 an bn ell n a n bn Output ircuit 6.8 (a) N i = i = ( i FB i ALL i )R i = i R i FB i R i ALL i R i alli FBi Ri i i N i lock 3

3 6.8 (b) N R O, N N 2, N N 2 N N 2 UP FS 2 UP F R2 O N 2 R2 O, S N N 2 N, N 2 F R O N N 2 OWN Name S Meaning aying on first floor Moving from first to second floor aying on second floor Moving from second to first floor FS OWN 6.8 (c) With the state assignment S =, =, =, =, we have: = F F ; 2 = F F N N 2 N N 2 R = F N ; R 2 = F N 2 ; UP =F N N 2 OWN = F N N 2 ; O = F F N N (a) H LRH H LH LRH LH S LH LH RH RH H - H H RH LRH RH H H H Outputs: L, LB, LA, RA, RB, R H 6.9 (b) First, assign L =, LB =, LA =, RA = 4, RB = 5, R = 6. So S =, =, =, etc. This state machine has too many state variables to use arnaugh maps. Instead, we will write down equations for each flip-flop by inspection. First consider. = in states or only. is reached whenever H = and we are not already in : H( ). But is the only state in which both = and 4 =, so assuming we are always in a valid state, we can use H( 4 ) = H H 4. Note: Any combination of one left light and one right light will also work, i.e. H H 5. is reached whenever we are in and L = while H = : LH But = whenever =, and 4 = 5 = 6 = whenever =. So we can use LH. 32

4 6.9 (b) (contd) So = LH H H 4 = L H H 4 (using Y = Y) Similarly = in states,, and only. and are reached whenever we are in or and L = while H =. LH LH = LH But again, 4 = 5 = 6 = whenever =, so 2 = L H H 4 We can also get by inspection: 3 = L 4 H H 4 ; 4 = R 6 H H 4 ; 5 = R 4 6 H H 4 ; 6 = R 5 6 H H (c) ate LRH = L LB LA RA RB R S S - - S S - - S S - - S S S - - S S - - S S - - S S S - - S S S S S S - - I. (S,,,,,, ) for in LRH =,, (,,,, ) for S in LRH = (,,,, ) for S in LRH = II. Every state matches S and. But S and match the best, so (S, ) (many times) III. (,,, ) (,,, ) etc. From LogicAid: So = H R H L H R 2 = RH RH LH 3 = LH LH RH L = ; LB = ; LA = R = ; RB = ; RA = Other minimum solutions can be found for 2 and 3 with this assignment. S 33

5 6.2 ST, FF RE RE FF PL PL ILE FF ST, FF, RE ST, RE Note: This state graph assumes that only one of the buttons ST, PL, RE, and FF can be pressed at any given time. The graph is incompletely specified and must be augmented before using LogicAid. For example, the arc from REW to PLAY should be labeled PL ST FF. ST REW R ST FF PL PL PL RE PLAY P ST RE FF PL PL FF FFW F ST RE PL ST ST M ST M SBA R ST M ST M SFW F ST RE FF PL M PLA P R F = ST FF PS ST RE PL ST M 2 = ST FF ST RE ST RE PL ST FF PL 3 = ST RE FF ST RE FF ST FF PL ST RE ST M ST ST RE PL P = ; R = ; F = lock 6.2 (a) S, 34

6 6.2 (b) ate Next ate x i = x i = S S a i b i a i b i x i = x i = b i a i S x i a i b i a i = (x i a i ) (x i b i ) x i a i b i b i = (x i b i ) (x i a i ) a n b n = a n 6.2 (c) a = b = a = (x ) (x ) = x b = (x ) (x ) = x 6.2 (d) x x 2 x n x a b ell a 2 a 3 b2 ell 2 b3 an bn ell n a n bn Unit 7 Problem Solutions 7. See FL p. 664 for solution. 7.2 See FL p. 665 for solution. 7.3 (a, b) (7)(6)(5)(4) (3)(2)()() O L O Up/own ENT LRn LOA ENP UP O L O Up/own LRn LOA ENT ENP UP (7)(6)(5)(4) See FL p for solutions. (3)(2)()() 7.4 See FL p for solution. 7.5 See FL p. 667 for solution. 35

7 7.6 (a, b) See FL p for solutions ROM 2 2 L L 7.7 (a) See FL p. 668 for solution. () (2) E E A B L L A A() A B B() A A(2) A B B(2) 7.7 (b) () (2) E E A B L A L A A() B() A(2) B(2) 7.8 See FL p. 668 for solution. 36

8 7.9 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity srff is port (clk, s, r : in std_logic; q, qn : out std_logic); end srff; architecture Behavioral of srff is signal qint : std_logic:=; q <= qint; qn <= not qint; process(clk) if clkevent and clk= then if (not s and r)= then qint <= ; elsif (s and not r)= then qint<=; elsif (s and r)= then qint<=; end if; end if; end Behavioral; 7. library IEEE; 7. A rising edge triggered -E flip flop with asynchronous clear and preset. use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; -- -G Latch entity dglatch is port (d, g : in bit; q : out bit); end dglatch; architecture Behavioral of dglatch is process(g, d) if g= then q <= d; end if; end Behavioral; -- flip flop using -G latches library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity dff is port (d, clk : in bit; q : out bit); end dff; architecture Behavioral of dff is component dglatch is port (d, g: in bit; q : out bit); end component; signal p, clkn : bit; clkn <= not clk; dg : dglatch port map(d, clkn, p); dg2 : dglatch port map(p, clk, q); end Behavioral; 7.2 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; 8 use IEEE.ST_LOGI_UNGNE.ALL; En entity myreg is int port(en, ld, clk : in std_logic; 8 d : in std_logic_vector(7 downto ); q : out std_logic_vector(7 downto )); 8-bit Register end myreg; architecture Behavioral of myreg is 8 signal qint : std_logic_vector(7 downto ):=""; q <= qint when en = else ""; process(clk) if clk event and clk= then if ld= then qint <= d; end if; end if; end Behavioral; 37

9 7.3 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity encoder is port (y, y, y2, y3 : in bit; a, b, c : out bit); end encoder; architecture Behavioral of encoder is process(y, y, y2, y3) if y3= then a <= ; b <= ; c <= ; -- y3 has highest priority elsif y2= then a <= ; b <= ; c <= ; elsif y= then a <= ; b <= ; c <= ; elsif y= then a <= ; b <= ; c <= ; else a <= ; b <= ; c <= ; end if; end Behavioral; 7.4 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity comparator is port (a, b : in std_logic_vector(3 downto ); agb, alb, aeb : out std_logic); end comparator; architecture Behavioral of comparator is process(a, b) if a > b then agb <= ; alb <= ; aeb <= ; elsif a < b then agb <= ; alb <= ; aeb <= ; else agb <= ; alb <= ; aeb <= ; end if; end Behavioral; 7.5 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity super is port (a: in std_logic_vector(2 downto ); d : in std_logic_vector(5 downto ); rsi, lsi, clk : in std_logic; q : out std_logic_vector(5 downto )); end super; architecture Behavioral of super is signal qint: std_logic_vector(5 downto ); q <= qint; process(clk) if clk event and clk= then case a is when ""=> qint <= d; when ""=> qint <= qint-; when ""=> qint <= qint; when ""=> qint <= ""; when ""=> qint <= ""; 7.6 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity bcd_seven is port (bcd : in bit_vector(3 downto ); seven : out bit_vector(7 downto )); end bcd_seven; architecture Behavioral of bcd_seven is process(bcd) case bcd is when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> seven <= ""; when ""=> qint <= rsi&qint(5 downto ); when ""=> qint <= qint(4 downto )&lsi; when others=> NULL; end case; end Behavioral; end case; end if; end Behavioral; 38

10 7.7 library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity sm is port (x, clk : in std_logic; z : out std_logic); end sm; architecture Behavioral of sm is type rom8_3 is array( to 7) of std_logic_vector( to 2); constant myrom: rom8_3 :=("","","","","","", "",""); signal index, romout: std_logic_vector( to 2); signal q, d: std_logic_vector( to 2):=""; index <= x&q; romout <= myrom(conv_integer(index)); z <= romout(); d <= romout( to 2); process(clk) if clk event and clk= then q <= d; end if; end Behavioral; 7.8 S --The state assignment is as follows (qqq2q3)- --S - ; S - ; S2 - ; S3 - --VHL code using equations derived by inspection from state graph entity sm is port (x, clk : in bit; z : out bit); end sm; architecture equations of sm is signal q : bit := ; signal q, q2, q3 : bit:=; process(clk) if clkevent and clk= then q <= (x and q) or (not x and q) or (not x and q3); q <= (not x and q) or (x and q3); q2 <= (x and q2) or (x and q); q3 <= not x and q2; end if; z <= (not x and q) or (x and q3) or q2; end equations; 7.9 ate Next ate = = Output = = S S S S 7.2 ate Next ate = = Output S S S S 39

11 7.2 ate Next ate 2 = S S S S S 7.22 library IEEE; 7.23 ore Set M 8 8 Mask Register library IEEE; use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity Seq_43 is port (, : in std_logic; : out std_logic); end Seq_43; architecture Moore of Seq_43 is signal ate : integer := ; signal Nextate : integer range to 3; process(ate, ) case ate is when => <= ; if = then Nextate <= ; else Nextate <= ; end if; when => <= ; if = then Nextate <= 2; else Nextate <= ; end if; when 2 => <= ; if = then Nextate <= ; else Nextate <= 3; end if; when 3 => <= ; if = then Nextate <= 2; else Nextate <= ; end if; end case; process() if event and = then ate <= Nextate; end if; end Moore; 8 8 use IEEE.ST_LOGI_64.ALL; use IEEE.ST_LOGI_ARITH.ALL; use IEEE.ST_LOGI_UNGNE.ALL; entity mask_8 is port ( : in std_logic_vector(7 downto ); ore, Set, : in std_logic; : out std_logic_vector(7 downto )); end mask_8; architecture Behavioral of mask_8 is signal M : std_logic_vector(7 downto ); process(set, ) if Set= then M <= ""; elsif event and = then if ore= then M<=; end if; end if; <= M and ; end Behavioral; 4

12 Unit 8 Problem Solutions 8.3 See FL p. 669 for circuit. Notice that the output of the flip-flop is b in, while the input is b out. 8.4 See FL p. 67. AN-ing with x i is like M/Ad if x i is. ifting is like moving from AN gates involving x to those involving x 2, or from x 2 to x See FL p. 67. ompare to divider state graph of FL Figure 8-. S 8.6 See FL p (a) Overflow occurs only on division by, so V = y y y 2 y 3 y 4 = (y y y 2 y 3 y 4 ) 8.7 (b) - (d) See FL p See FL p The ONE AER is similar to a serial adder, except that there is only one input. This means that the carry will be added to. Thus, if the carry flip-flop is initially set to, will be added to the input. The signal I can be used to preset the carry flip-flop to. Let S represent arry =, and let represent arry =. The state graph is as follows:, I, S I PreN = ( ) = ( ) () ( ) = ( ) () ( ) or 4

13 8. (a) product O N T R O L M Load Ad one 7 4 A BIT AER multiplier multiplicand 8. (b) 8. (c) / - /one S /Load S9 S7 - / M/Ad M/ M/ add shift shift add shift M/Ad M/ S3 - / - / S4 M/Ad 8. (d) Present ate Next ate M: Ad Load one S S S S S S S I. (S, ) (, ) (, ) (, ) II. (S, ) (, ) (, ) (, ) III. (,, ) (,, ) etc. A B S (Other assignments are possible.) 42

14 8. (d) For this assignment, from LogicAid: (contd) J A = B M; A = M B ; J B = A; B = A; J = AB; = AB; Ad = MAB MA; = MA M AB A; Load = AB; one = AB M M Ad OR gates, AN gates, & inverters implement the equations from 8. (d) adder 4 5 multiplicand Ad one J A 3 3 multiplier J J B 8. (a) product O N T R O L M Load Ad one 8 5 A BIT AER multiplier multiplicand 43

15 8. (b) See solution to 8. (b). 8. (d) Graph is same as 8., so from LogicAid, using the same state assignment: A = AB MAB MA B = A AB = AB B A 8. (c) shift add shift add shift Ad,,, one: See solution to 8. (d) M A B A B Ad one M A B PLA Ad one M Ad FA FA FA FA FA multiplier multiplicand 44

16 8.2 (a) S Ad M M M 8.2 (b) ate ounter M Ad S S M M Ad 8.3 (a) (alternate solution) d 7 d 6 d 5 b 8 Full Subtracter b 7 Full Subtracter b 6 Full Subtracter b 5 = x 7 x 6 x 5 y 2 y divisor 8.3 (b) x 7 x 6 x 5 x 4 x 3 x 2 x x Subtracter- omparator Su ontrol V ivisor 8.3 (d) shift = sub. = shift = sub. = shift = shift = sub. = shift = sub. = = 8.3 (c) Su, S Su V Su Su Su remainder quotient 45

17 8.4 (a) 8.4 (b) x 7 x 6 x 5 x 4 x 3 x 2 x Subtracter- omparator y 4 y 3 y 2 y Su ontrol V S V Su, Su 8.4 (c) alternate solution d 7 d 6 d 5 d 4 d 3 omparator omparator F.A. F.A. F.A. F.A. F.A. x 7 x 6 y 4 x 5 y 3 x 4 y 2 x 3 y 8.4 (d) 8.5 (a) shift = sub. = shift = sub. = S R B B B B remainder quotient 8.5 (b) = ; = B B ; 2 = B B ; R = = B B B B = ; = B B = B B 8.6 (a) S o lr ounter 8.6 (b) S o S o Er S, lr ontroller S o Er S o So S o, 46

18 8.6 (c) = ; = ; 2 = ; lr= = ; Er= ; = 8.7 (a) ontrol ounter ift Register A ift Register B a b Logic Network 8.7 (b) S Present ate S S S S S 8.7 (c) I. (S, ) 2 (, ) (S, ) II. (S, ) 2 (, ) (S, ) 2 From arnaugh maps: S 8.7 (d) = ab ab ab = = = = ; = Alternative: = (a) ontrol ounter ift Register A ift Register B a b Logic Network 8.8 (b) S ate S Meaning Reset Find AN of A & B Find OR of A & B 47

19 8.8 (c) = ; = ; = ; = = (d) hange to in 8.7 (d) = ab ab ab 8.9 (b) - - S (a) Note: M can be determined independently of the state of the system, so it is not included in the state graph. 8.2 (a) ontrol M A B (c) J A = B; A = B; J B = A; B = ; ounter = A B; M = 2 2 ontroller 3 N 8.2 (b) B S S A 8.2 (c) ate AB S S S S = ; 2 = ; A = ; B = ; = 8.2 Ac, EnIn EnIn, Ad S EnAd, Ac ontrol EnAd Ad EnIn Ac one one one, EnAd, Ac EnIn, Ad 48

20 8.22 (a) ER ER (b) J = ST; = ER ER2; T2 L one = ER ER2 ; LR = ST; ER ER2 L2 = ST; L = ST ER ER2 ; one S S T = ER ; T2 = ER ER2 L2 L LR 8.22 (c) (N )N 2 cycles ER T 8.23 (a) S EERO one LR LOA IERO EERO OWN 8.23 (b) = EERO ; one = EERO ; LR = ; LOA = IERO EERO OWN = IERO EERO UP = IERO EERO IERO EERO 8.23 (d) The quotient counter reaches, and UP = UP LOA again (c) N (N /N 2 ) cycles (round down) 8.23 (e) The quotient will count upward forever, and one will never be N 8 ontrol ircuit Su Su 8-bit register 8 8 B 8-bit subtracter 8 "" 4 lr Inc 4-bit counter - start - load N into register and clear counter Su - load subtracter output into register Inc - increment counter B - borrow odd integer When the done signal comes on, square root is in the 4-bit counter B Su Inc S B one 49