CSE140: Design of Sequential Logic

Transcription

1 CSE4: Design of Sequential Logic Instructor: Mohsen Imani

2 Flip Flops 2

3 Counter 3

4 Up counter 4

5 Up counter 5

6 FSM with JK-Flip Flop 6

7 State Table 7

8 State Table 8

9 Circuit Minimization 9

10 Circuit

11 Timing Constraints in Sequential Designs

12 Timing Constraints in Sequential Circuit Designs Combinational CLK Our seemingly logically correct design can go wrong signals don t travel in zero time We next look at timing constraints for combinational and sequential logic.

13 Combinational Logic Timing I. Min delay of a gate, also called contamination delay: t cd Minimum time from when an input changes until the output starts to change II. Max delay of a gate, also called propagation delay: t pd Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing) 3

14 Combinational Logic: Output Timing Constraints A B C D Y Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both D. Neither 4

15 Combinational Logic: Output Timing Constraints A B C D Y Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both D. Neither 5

16 D-FF Input Constraints: Setup and Hold Times D S D latch D Q Q CLK C D R Q D S D latch t setup t hold C Q t a R I. Setup time: t setup Time before the clock edge that data must be stable (i.e. not change) II. Hold time: t hold Time after the clock edge that data must be stable Aperture time: t a Time around clock edge that data must be stable (t a = t setup + t hold ) 6

17 Output Timing Constraints D Q Q CLK Q t ccq t pcq I. Min delay of FF, also called contamination delay or min CLK to Q delay: t ccq Time after clock edge that Q might be unstable (i.e., starts changing) II. Max delay of FF, also called propagation delay or maximum CLK to Q delay: t pcq Time after clock edge that the output Q is guaranteed to be stable (i.e. stops changing) 7

18 The timing of which of the following signals can cause a setup-time violation? A. The input signal D(t) B. The output signal Q(t) C. Both of the above D. None of the above Comb Logic D(t) D Q Q Q(t) CLK 8

19 Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) CLK R Q C L T c D2 CLK R2 Which of the following violations occurs if max delay of R is zero & max delay of the combinational circuit is equal to the clock period? CLK Q D2 (b) A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R D. Setup violation for R E. None of the above

20 Setup Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay CLK CLK Q C L D2 (a) R R2 Setup time constraint: T c T c t setup + max delay(ff) + CLK max delay(combinational) Q D2 (b) T c t pcq + t pd + t setup

21 Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) CLK R Q C L D2 CLK R2 Which of the violations would occur if the min delay of R was zero and the combinational circuit was just a wire? CLK Q D2 (b) T c A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R D. Setup violation for R E. None of the above

22 Hold Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay CLK CLK Q C L D2 (a) R R2 Hold time constraint: T c t hold < min delay(ff) + CLK min delay(combinational) Q t hold < t ccq + t cd D2 (b)

23 FF Timing Parameters Once a flip flop has been built, its timing characteristics stay fixed: t setup, t hold, t ccq, t pcq D Q D2 R Combinational R2 CLK CLK What about the clock? Does the clock edge arrive at the same time to all the D-FFs on the chip? 23

24 Clock Skew The clock doesn t arrive at all registers at the same time Skew: difference between the two clock edges Perform the worst case analysis C LK delay Q C D 2 L C LK C LK 2 R R 2 t skew C LK C LK 2 C LK

25 Setup Time Constraint with Skew In the worst case, CLK2 is earlier than CLK t pcq is max delay through FF, t pd is max delay through logic CLK CLK2 Q C L D2 CLK CLK2 Q D2 R T c R2 T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) t pcq t pd t setup t skew

26 Hold Time Constraint with Skew In the worst case, CLK2 is later than CLK t ccq is min delay through FF, t cd is min delay through logic CLK Q C L D2 CLK2 CLK CLK2 R R2 t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq Q D2 t ccq t cd t skew t hold

27 Summary on timing constraints R Combinational R2 Combinational: - Maximum delay = Propagation delay - Minimum delay = Contamination delay Flip Flops: - Input: - Setup time - Hold time - Output: - Propagation clock-to-q time - Contamination clock-to-q time Once the logic/ffs are built, these timing characteristics are fixed properties

28 Summary on timing constraints R Combinational R2 Constraint inequalities: - Without clock skew: + + < + Setup time constraint Hold time constraint - With clock skew: < +

29 Timing Analysis Example CLK A B C X' CLK X Timing Characteristics t ccq t pcq = 3 ps = 5 ps t setup = 6 ps t hold = 7 ps D t pd = 3 x 35 ps = 5 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 25 ps f c = /T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? (3 + 25) ps > 7 ps? No!

30 Timing Analysis Example Add buffers to the short paths: CLK A B C X' CLK X Timing Characteristics t ccq t pcq t setup t hold = 3 ps = 5 ps = 6 ps = 7 ps D t pd = 3 x 35 ps = 5 ps t cd = 2 x 25 ps = 5 ps Setup time constraint: T c ( ) ps = 25 ps f c = /T c = 4.65 GHz Y' Y per gate t pd t cd Hold time constraint: t ccq + t cd > t hold? = 35 ps = 25 ps Does it satisfy hold time constraint? A. Yes B. No (3 + 5) ps > 7 ps? Yes!

31 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C AND 2ns ns NOT ns ns XOR ns 5ns FF 2ns 3ns ns 7ns What s the maximum frequency? A. / ns B. / 22ns C. / 2ns D. / 8ns E. None of the above

32 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C ) Assume =, find the maximum frequency + + = ( + 2) = = 4.5MHz 22

33 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C FF 2ns 2) Does the circuit have a hold violation? A. Yes B. No C. I don t know AND 2ns ns NOT ns ns XOR ns 5ns 3ns ns 7ns < + 3 < Hold time violation!

34 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C 3) Where to place a buffer with = = 25 to solve this hold time violation? A. After A B. After B C. After C D. Before D E. Before E < + 3 < Hold time violation solved!

35 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C 4) Assume = 2, find the maximum frequency = = = 4.6MHz 24

36 Example: timing constraints D Q D-FF A D D Q D-FF D Q D-FF B E D Q D-FF D Q D-FF C 5) Assume = 2 and the additional buffer, do we have a hold time violation? + < < Hold time violation!

37 Sequential Circuit Design Summary SR Latch, D Latch, D-FF Design procedure for FSMs. Capture FSM 2. Create state table 3. Assign the states 4. Excitation table 5. Implement the combinational logic Mealy vs. Moore FSM Non-ideal properties of FFs Setup/hold time constraints Maximum operating frequency Clock skew 37

38 MORE FSM EXAMPLES TO DO AT HOME 38

39 5 cents for candy! Watch out no change! Moore machine outputs associated with state Reset N D + Reset Mealy machine outputs associated with transitions Reset/ (N D + Reset)/ [] N D N D / N N/ D 5 [] N D D/ 5 N D / N N/ D [] N D D/ N D / N+D N+D/ 5 [] Reset 5 Reset / 39

40 Example: Moore implementation D D Encode states and map to logic Q D Q Open Q N N N X X X X X X X X X D D Q Q Q present state inputs next state output Q Q D N D D open 4

41 Example: Mealy implementation Reset/ Reset/ N/ D/ 5 N/ D/ N+D/ 5 N D / N D / N D / Reset / Open Q D X X X Q N present state inputs next state output Q Q D N D D open 4

42 FSM design: Multiple input counter Given FSM of a multiple input counter, design the circuit implementing its functionality S S2, S S3 present next state output state S S S S2 S3 S S S3 S S3 S3 S S S S3 S2 S S3 S2 S State Input Inputs State 42

43 Multiple input counter: Logic for D-FF Derive logic equations for inputs of State D-FF Input D II D II 43

44 CSE4: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Slides from Tajana Simunic Rosing

45 High-Level State Machine Some behaviors may be too complex to describe by using classical FSMs Soda dispenser c: bit input, when coin deposited a: 8-bit input: value of the deposited coin s: 8-bit input: cost of a soda d: bit output, processor sets it to when total value of deposited coins equals or exceeds cost of a soda c d 5 s a Soda dispenser processor tot: 5 25

46 Challenges in High-Level State Machines 5.2 Which of the following makes the FSM design of this problem difficult? A. 8-bit input/output B. Tracking the current total C. Multibit comparison D. All of the above E. None of the above c d c d s Soda dispenser processor 5 s a Soda dispenser processor a tot:

47 Benefits of HLSMs s a 8 8 High-level state machine (HLSM) extends FSM with: Multi-bit input/output Local storage Arithmetic operations Conventions Numbers: Single-bit: '' (single quotes) Integer: (no quotes) Multi-bit: (double quotes) == for comparison equal Multi-bit outputs must be registered via local storage // precedes a comment c d Soda dispenser processor Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '' dispenses soda Local storage: tot (8 bits) Init d:='' tot:= SodaDispenser Wait c Add c' (tot<s) tot:=tot+a Disp d:='' 47

48 Benefits of HLSMs s a 8 8 High-level state machine (HLSM) extends FSM with: Multi-bit input/output Local storage Arithmetic operations Conventions Each transition is implicitly ANDed with a rising edge of the clock Any bit output not explicitly assigned a value in a state is implicitly assigned to. This convention does not apply for multibit outputs Every HLSM multibit output is registered c d Soda dispenser processor Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '' dispenses soda Local storage: tot (8 bits) Init d:='' tot:= SodaDispenser Wait c Add c' (tot<s) tot:=tot+a Disp d:='' 48

49 FSMs vs. HLSMs s a 8 8 a How does the HLSM differ from the FSM for this problem? A. The HLSM stores multibit data, but the FSM doesn t B. The FSM stores the state but the HLSM doesn t C. Implementing HLSM and FSM requires multibit data registers D. All of the above E. None of the above c d Soda dispenser processor Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '' dispenses soda Local storage: tot (8 bits) Init d:='' tot:= Wait c Add c *(tot<s) c' (tot<s) tot:=tot+a Disp SodaDispenser d:='' 49

50 Similarities between FSMs & HLSMs s a 8 8 Which of the following are common between HLSMs and FSMs? A. Transitions happen at the edge of a clock B. They both have external complex data C. All of the above D. None of the above c d Soda dispenser processor Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '' dispenses soda Local storage: tot (8 bits) Init d:='' tot:= Wait c Add c *(tot<s) c' (tot<s) tot:=tot+a Disp SodaDispenser d:='' 5

51 RTL Design Process Step : Capture a high-level state machine - Describe the system s desired behavior as a high-level state machine. The state machine consists of states and transitions. The state machine is high level because the transition conditions and the state actions are more than just Boolean operations on single-bit input and outputs Recommendations: - Always list all inputs, outputs and local registers on top of your HLSM diagram - Clearly specify the size in bits of each of them - On states: update the value of registers, update of outputs - On transitions: express conditions in terms of the HLSM inputs or state of the internal values and arithmetic operations between them. 5

52 RTL Design Process Step 2: Convert it to a circuit - 2.a: Create a datapath - Create a datapath to carry out the data operations of the high level state machine - Elements of your datapaths can be registers, adders, comparators, multipliers, dividers, etc. DP control inputs... External data inputs... Datapath... External data outputs 52

53 Datapath components: RTL Design Process clr I A B A B ld reg add cmp Q S lt eq gt I shift<l/r> Q I I mux2x s Q clk^ and clr=: Q= clk^ and ld=: Q=I else Q stays same S = A+B (unsigned) A<B: lt= A=B: eq= A>B: gt= shiftl: << shiftl2: <<2 shiftr: >>... s=: Q=I s=: Q=I A B sub S S = A-B (signed) A B mul P P = A*B (unsigned) A abs Q (signed) Q = A (unsigned) clr inc upcnt Q clk^ and clr=: Q= clk^ and inc=: Q=Q+ else Q stays same W_d W_a W_e R_a R_e R_d RF clk^ and W_e=: RF[W_a]= W_d R_e=: R_d = RF[R_a]

54 RTL Design Process Step 2: Convert it to a circuit - 2.b: Connect the datapath to a controller - Connect the datapath to a controller block. Connect the external control inputs and outputs to the controller block. - Clearly label all control signals that are exchanged between the datapath and the controller External control inputs External control outputs Controller DP control inputs DP control outputs External data inputs... Datapath... External data outputs 54

55 RTL Design Process Step 2: Convert it to a circuit - 2.c: derive the controller s FSM - Convert the high-level state machine to a finite state machine (FSM) for the controller, by replacing data operations with setting and reading of control signals to and from the datapath External control inputs External control outputs Controller DP control inputs DP control outputs External data inputs... Datapath... External data outputs The controller FSM should have: - Inputs: - Ext control inputs - DP control outputs - Outputs: - Ext. control outputs - DP control inputs 55

56 RTL Design Process: summary Capture the behavior with HLSM Convert it to a circuit High-level architecture (datapath and control path) Datapath capable of HLSM's data operations Design controller to control the datapath External control inputs External control outputs Controller DP control inputs DP control outputs External data inputs... Datapath... External data outputs

57 Step 2.a: Create Datapath for Soda Dispenser Need tot register to keep track of the money deposited so far Need 8-bit comparator to compare s (current sum) and a (target cost) Need 8-bit adder to update: tot = tot + a Connect everything Create control IO tot_ld tot_clr s 8 ld clr Inputs: c (bit), a(8 bits), s (8 bits) Outputs : d (bit) Local registers: tot (8 bits) tot Init d= tot= 8 a c 8 Wait (tot<s) c Add c (tot<s) tot= tot+a Disp d= tot_lt_s Datapath 8-bit < 8-bit adder 8

58 Signals in Soda Dispenser Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) // '' dispenses soda Local storage: tot (8 bits) s a c Add tot_ld tot_clr ld clr tot Init Wait tot:=tot+a a d:='' tot:= SodaDispenser c *(tot<s) c' (tot<s) Disp d:='' tot_lt_s Datapath 8-bit < 8-bit adder 8 According to the current design, under which of the following conditions does the register output tot change at the rising clock edge? A.Whenever the value of the coin inserted ( a ) changes B.Whenever the cost of the soda ( s ) changes C.When the signal tot_ld becomes high D.When the signal tot_clr becomes high E.Both C. & D. a

59 Step 2.b: Connect Datapath to a Controller s a Controller s inputs External input c (coin detected) Input from datapath comparator s c output, which we named tot_lt_s Controller s outputs External output d (dispense soda) Outputs to datapath to load and clear the tot register d Controller tot_ld tot_clr tot_lt_s s a 8 8 Datapath tot_ld tot_clr tot_lt_s 8 Datapath ld clr 8-bit < tot 8 8-bit adder 8 8

60 Step 2.c Derive the Controller s FSM FSM has the same states and arcs as HLSM Replace all references to the data elements in the HLSM with appropriate control signals & values c d Controller tot_ld tot_clr tot_lt_s s a 8 8 Datapath s a c d Inputs: :c,tot_lt_s(bit) Outputs:d,tot_ld,tot_clr(bit) Init d= tot_clr= Wait c Add tot_ld= c * tot_lt_s Disp tot_ld tot_clr tot_lt_s tot_ld tot_clr tot_lt_s 8 ld clr 8-bit < Datapath tpt 8 8-bit adder 8 8 Controller d=

61 Final Step: Implement the controller FSM Implement the FSM as a state register and logic I n p u t s : : c, tot_lt_s (bit) s s c tot_lt_s n n d tot_ld tot_clr Outputs: d, tot_ld, tot_clr (bit) c d Init d= tot_clr= Wait c Add tot_ld= c * tot_lt_s Disp tot_ld tot_clr tot_lt_s Init Wait Add Controller d= Disp

62 Another RTL Design: Laser-Based Distance Measurer T (in seconds) laser sensor D 2D = T sec * 3* 8 m/sec Object of interest Laser-based distance measurement pulse laser, measure time T to sense reflection Laser light travels at speed of light, 3* 8 m/sec Distance is thus D = T sec * 3* 8 m/sec / 2

63 Laser-Based Distance Measurer IO T (in seconds) laser B from button L to laser sensor D to display 6 Laser-based distance measurer S from sensor Inputs/outputs B: bit input, from button, to begin measurement L: bit output, activates laser S: bit input, senses laser reflection D: 6-bit output, to display computed distance 63

64 Laser-Based Distance Measurer: HLSM DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (6 bits) Local storage: Dreg(6) from button B D to display 6 Laserbased distance measurer L to laser S from sensor a S? L := '' // laser off Dreg := // distance is (first state usually initializes the system) Declare inputs, outputs, and local storage Dreg required for multi-bit output Create initial state, name it S Initialize laser to off (L:='') Initialize displayed distance to (Dreg:=) Recall: '' means single bit, means integer 64

65 Laser-Based Distance Measurer: HLSM DistanceMeasurer... B' // button not pressed from button B D to display 6 Laserbased distance measurer L to laser S from sensor S L := '' Dreg := S B? // button pressed Add another state, S, that waits for a button press B' stay in S, keep waiting B go to a new state S2 65

66 Laser-Based Distance Measurer: HLSM DistanceMeasurer... B' from button B D to display 6 Laserbased distance measurer L to laser S from sensor S S B S2 S3 L := '' Dreg := L := '' // laser on L := '' // laser off Add a state S2 that turns on the laser (L:='') Then turn off laser (L:='') in a state S3 66

67 Laser-Based Distance Measurer: HLSM DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (6 bits) Local storage: Dreg, Dctr (6 bits) B' S' // no reflection B from button D to display 6 Laser-based distance measurer L to laser S from sensor S S S2 S3 B L := '' Dreg := Dctr := // reset cycle count L := '' L := '' Dctr := Dctr + // count cycles S // reflection? a Stay in S3 until sense reflection (S) To measure time, count cycles while in S3 To count, declare local storage Dctr Initialize Dctr to in S. In S2 would have been O.K. too. Don't forget to initialize local storage common mistake Increment Dctr each cycle in S3 67

68 Laser-Based Distance Measurer: HLSM DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (6 bits) Local storage: Dreg, Dctr (6 bits) B' S' B from button D to display 6 Laserbased distance measurer L to laser S from sensor S S S2 S3 B L := '' Dreg := Dctr := L := '' S L := '' Dctr := Dctr+ S4 Dreg := Dctr/2 // calculate D a Once reflection detected (S), go to new state S4 Calculate distance Assuming clock frequency is 3x 8, Dctr holds number of meters, so Dreg:=Dctr/2 After S4, go back to S to wait for button again 68

69 Laser-Based Distance Measurer: Create a Datapath DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (6 bits) Local storage: Dreg, Dctr (6 bits) B' S' S S S2 S3 B L := '' Dreg := Dctr := L := '' S L := '' Dctr := Dctr+ S4 Dreg := Dctr/2 // calculate D 6 Datapath HLSM data I/O DP I/O HLSM local storage reg HLSM state action and transition condition data computation Datapath components and connections Dreg_clr Dreg_ld Dctr_clr Dctr_ld A B Add: add(6) S 6 clr I ld Dctr: reg(6) Q 6 I Shr: shiftr(6) Q 6 clr ld I Dreg: reg(6) Q D 6 69

70 Laser-Based Distance Measure: Connecting the Datapath to a Controller from button B Controller Dreg_clr L S to laser from sensor Dreg_ld Dctr_clr Datapath to display D 6 3 MHz Clock Dctr_ld 7

71 DistanceMeasurer Laser-Based Distance Measurer: Derive the Controller FSM S S S2 S3 B L := '' Dreg := B' Inputs: B (bit), S (bit) Outputs: L (bit), D (6 bits) Local storage: Dreg, Dctr (6 bits) Dctr := HLSM L := '' S' S L := '' Dctr := Dctr+ S4 Dreg := Dctr/2 // calculate D Dreg_clr Dreg_ld Dctr_clr Dctr_ld D clr ld 6 A B Add: add(6) S 6 I Dctr: reg(6) Q 6 Datapath I Shr: shiftr(6) Q 6 clr I ld Dreg: reg(6) Q 6 FSM has same states, transitions, and control I/O Achieve each HLSM data operation using datapath control signals in FSM Controller B Inputs: B, S B S S S2 S3 L = L = L = L = Dreg_clr = Dreg_clr = Dreg_ld = Dreg_ld = Dctr_clr = Dctr_clr = Dctr_ld = Dctr_ld = (clear count) (laser on) Dreg_clr = Dreg_ld = Dctr_clr = Dctr_ld = (laser off) (clear Dreg) Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld S S Dreg_clr = Dreg_ld = Dctr_clr = Dctr_ld = (laser off) (count up) S4 L = Dreg_clr = Dreg_ld = Dctr_clr = Dctr_ld = (load Dreg with Dctr/2) (stop counting) 7

72 Laser-Based Distance Measurer: Simplify the Controller FSM Controller Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld B S B S S S2 S3 L = Dctr_clr = L = L = Dreg_clr = (clear count) (laser on) Dctr_ld = (laser off) (laser off) (clear Dreg) (count up) S S4 Dreg_ld = Dctr_ld = (load Dreg with Dctr/2) (stop counting) Same FSM, using convention of unassigned outputs implicitly assigned Some assignments to still shown, due to their importance in understanding desired controller behavior 72