Experiment 4 Decoder Encoder Design using VHDL

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Angel Kelley
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1 Objective: Experiment 4 Decoder Encoder Design using VHDL To learn how to write VHDL code To Learn how to do functional simulation To do study of the synthesis done by VHDL and the theoretical desin obtained using algebraic solution. Requirement: A computer system installed with XILINX VHDL Theory: A decoder generally decodes a binary value into a non-binary one by setting exactly one of itsn outputs to logic 1. If a binary decoder receives n inputs (usually grouped as a single binary or Boolean number) it activates one and only one of its 2 n outputs based on that input with all other outputs deactivated. The truth table of a decoder is shown below: S1 S0 O0 O1 O2 O As seen in the truth table only one of the output line is active depending on the input line combination. The logic equations for a decoder can be written as: O0 : S 1 S 0 1 when S 1 =0 and S 0 =0 O1 : S 1 S 0 1 when S 1 =0 and S 0 =1 O2 `: S 1 S 0 1 when S 1 =1 and S 0 =0 O3 : S 1 S 0 1 when S 1 =1 and S 0 =1 Now using the above expressions we can write the VHDL code for any size of decode. Here we implement a 1: 2 decoder with and without enable input. Then use thse as building block for constructing larger size deciders.

2 Synthesis 1 Decoder without enable library IEEE; use IEEE.STD_LOGIC_1164.ALL; entitydecod is Port ( sel : in STD_LOGIC; o1 : out STD_LOGIC; o2 : out STD_LOGIC); enddecod; architecture Behavioral of decod is o2 <= '1' when sel='1' else '0' when sel='0'; withsel select o1 <= '1' when '0', '0' when '1', 'Z' when others; 2 Decoder with enable input library IEEE; use IEEE.STD_LOGIC_1164.ALL; entitydecoder_with_enable is Port ( sel : in STD_LOGIC; en : in STD_LOGIC; o1 : out STD_LOGIC;

3 o2 : out STD_LOGIC); enddecoder_with_enable; architecture Behavioral of decoder_with_enable is o1 <= '1' when sel='0' and en='1' else '0'; o2 <= '1' when sel='1' and en='1' else '0'; 3A 2:4 Decoder using 1:2 Decoder in structure modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder2to4_structure is Port ( I : in STD_LOGIC_VECTOR (1 downto 0);

end decoder2to4_structure; o : out STD_LOGIC_VECTOR (3 downto 0)); architecture Behavioral of decoder2to4_structure is signal w1, w2: std_logic; RTL View: x1: entity work.

4 end decoder2to4_structure; o : out STD_LOGIC_VECTOR (3 downto 0)); architecture Behavioral of decoder2to4_structure is signal w1, w2: std_logic; RTL View: x1: entity work.decod PORT MAP (sel=>i(1), o1=> w1,o2=> w2); x2: entity work.decoder_with_enable PORT MAP (sel=>i(0), en=> w1, o1=> o(0), o2=> o(1)); x3: entity work.decoder_with_enable PORT MAP (sel=>i(0), en=> w2,o1=> o(2), o2 => o(3)); The snapshot shows the top level design of 1 2:4 decoder wit I(1:0) being the inputs and o(3:0) being the outputs. Simulation

5 2. ENCODER An encoder accepts an active level on one of its inputs, representing digit, such as a decimal or octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding. An encoder has a number of input lines, only one of which input is activated at a given time and produces an N-bit output code,depending on which input is activated. The functional table for a 4 line to 2 line encoder is shown below: Inputs Output K0 K1 K2 K3 Yo Y The Boolean equations for coded outputs are: Y0= k2+k3 Y1= K1 + K3

6 Priority Encoder A priority Encoder encodes one of the many inputs but only the key having the highest priority is encoded first. If highest priority key is not pressed then the next lower priority key is encoded and so on. The functional table is given below, In the table Y0Y1 are the encoded output, output V is an indicator of a valid key press and is high when one of the valid key is pressed: K0 K1 K2 K3 Y0 Y1 V x x x x x x x x The first row in table shows none of the key pressed, so the output (Y0, Y1) are don t care, and V output is zero indicating none of the valid key pressed. The other rows shows only one input is active and the least numbered keys are don t cared, and a valid key press entry V is raised and corresponding binary output obtained at Y1, Y1. The Boolean equations are: The equation for V is: V = K0 + K1 + K2 + K3 The logic diagram for the 4 to 2 priority encoder is shown in figure below:

7 VHDL Code for 4:2 priority encoder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PRIORITY_ENCODER is Port ( K : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC_VECTOR (1 downto 0); V : out STD_LOGIC); end PRIORITY_ENCODER; architecture Behavioral of PRIORITY_ENCODER is Y(0) <= K(2) OR K(3); Y(1) <= (K(3) OR (K(1) AND (not K(2)))); V <= K(0) OR K(1) OR K(2) OR K(3); Schematic View

8 Simulation: Structural Modelling of 4:2 Priority Encoder entity or_4ip is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); o : out STD_LOGIC); end or_4ip; architecture Behavioral of or_4ip is o <= i(0) or i(1) or i(2) or i(3); entity OR_GATE is Port ( i1 : in STD_LOGIC;

9 i2 : in STD_LOGIC; o : out STD_LOGIC); end OR_GATE; architecture Behavioral of OR_GATE is o <= i1 or i2; entity NO_GATE is Port ( i : in STD_LOGIC; o : out STD_LOGIC); end NO_GATE; architecture Behavioral of NO_GATE is o <= not i; library IEEE; use IEEE.STD_LOGIC_1164.ALL; librarymy_logics_lib; usemy_logics_lib.all; entityencoder_structure is Port ( k : in STD_LOGIC_VECTOR (3 downto 0); o : out STD_LOGIC_VECTOR (1 downto 0);

v : out STD_LOGIC); endencoder_structure; architecture Behavioral of encoder_structure is signal w1, w2: std_logic; x1: entity work.or_gate port map (i1=>k(3), i2 => w1, o => o(1)); x2: entity work.

10 v : out STD_LOGIC); endencoder_structure; architecture Behavioral of encoder_structure is signal w1, w2: std_logic; x1: entity work.or_gate port map (i1=>k(3), i2 => w1, o => o(1)); x2: entity work.no_gate port map (i=> k(2), o => w2); x3: entity work.and_gate port map (i1=>k(1), i2 => w2, o => w1); x4: entity work.or_gate port map (i1=>k(2), i2 => k(3), o => o(0)) ; x5: entity work.or_4ip port map (i(0)=> k(0), i(1)=> k(1), i(2) => k(2), i(3) => k(3), o => v);

Acknowledgment. DLD Lab. This set of slides on VHDL are due to Brown and Vranesic.

Acknowledgment. DLD Lab. This set of slides on VHDL are due to Brown and Vranesic. Acknowledgment DLD Lab Thi et o lide on VHDL are due to Brown and Vraneic. Introduction to VHDL (Very High Speed Integrated Circuit Hardware Decription Language) 2 3 A imple logic unction and correponding