Acknowledgment. DLD Lab. This set of slides on VHDL are due to Brown and Vranesic.
|
|
|
- Godwin Morrison
- 5 years ago
- Views:
Transcription
1 Acknowledgment DLD Lab Thi et o lide on VHDL are due to Brown and Vraneic. Introduction to VHDL (Very High Speed Integrated Circuit Hardware Decription Language) 2 3 A imple logic unction and correponding VHDL code VHDL code or a our-input unction 3 2 g : OUT STD_LOGIC ) ; WITH SELECT <= w WHEN '', w WHEN OTHERS ; 4 Logic circuit or our-input unction Figure 6.27 VHDL code or a 2-to- multipleer
2 w w (a) Graphical ymbol w w (b) Truth table ENTITY mu4to IS PORT ( w, w, w2, w3 : IN STD_LOGIC ; : IN STD_LOGIC_VECTOR( DOWNTO ) ; : OUT STD_LOGIC ) ; END mu4to ; w w (c) Sum-o-product circuit w w (d) Circuit with tranmiion gate ARCHITECTURE Behavior OF mu4to IS WITH SELECT <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; Figure 6. A 2-to- multipleer Figure 6.28 VHDL code or a 4-to- multipleer w w w 2 (a) Graphic ymbol w w w w w 2 (b) Truth table PACKAGE mu4to_package IS COMPONENT mu4to PORT ( w, w, w2, w3 : IN STD_LOGIC ; : IN STD_LOGIC_VECTOR( DOWNTO ) ; : OUT STD_LOGIC ) ; END COMPONENT ; END mu4to_package ; w 2 (c) Circuit Figure 6.2 A 4-to- multipleer Figure 6.28 Component declaration or the 4-to- multipleer w w LIBRARY work ; USE work.mu4to_package.all ; ENTITY mu6to IS PORT ( w : IN STD_LOGIC_VECTOR( TO 5) ; : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; : OUT STD_LOGIC ) ; END mu6to ; w 2 ARCHITECTURE Structure OF mu6to IS SIGNAL m : STD_LOGIC_VECTOR( TO 3) ; Mu: mu4to PORT MAP ( w(), w(), w(2), w(3), ( DOWNTO ), m() ) ; Mu2: mu4to PORT MAP ( w(4), w(5), w(6), w(7), ( DOWNTO ), m() ) ; Mu3: mu4to PORT MAP ( w(8), w(9), w(), w(), ( DOWNTO ), m(2) ) ; Mu4: mu4to PORT MAP ( w(2), w(3), w(4), w(5), ( DOWNTO ), m(3) ) ; Mu5: mu4to PORT MAP ( m(), m(), m(2), m(3), (3 DOWNTO 2), ) ; END Structure ; Figure 6.3 Uing 2-to- multipleer to build a 4-to- multipleer Figure 6.29 Hierarchical code or a 6-to- multipleer
3 w w 4 w 7 w 8 w w 2 w ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; Figure 6.4 A 6-to- multipleer Figure 6.3 VHDL code or a 2-to-4 binary decoder En w w y y y 2 y 3 (a) Truth table w w w y w y y 2 En y 3 (b) Graphic ymbol y y y 2 : OUT STD_LOGIC ) ; <= w WHEN = '' w ; En (c) Logic circuit y 3 Figure 6.6 A 2-to-4 decoder Figure 6.3 A 2-to- multipleer uing a conditional ignal aignment PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; y <= "" WHEN w(3) = '' "" WHEN w(2) = '' "" WHEN w() = '' "" ; z <= '' WHEN w = "" '' ; w 2 w w y y d d z Figure 6.32 VHDL code or a priority encoder Figure 6.24 Truth table or a 4-to-2 priority encoder
4 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; WITH w SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; WITH w SELECT z <= '' WHEN "", '' WHEN OTHERS ; Figure 6.33 Le eicient code or a priority encoder USE ieee.td_logic_unigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS AeqB <= '' WHEN A = B '' ; AgtB <= '' WHEN A > B '' ; AltB <= '' WHEN A < B '' ; Figure 6.34 VHDL code or a our-bit comparator a 3 i 3 b 3 a 2 b 2 i 2 i AeqB USE ieee.td_logic_arith.all ; a b a b i AltB ENTITY compare IS PORT ( A, B : IN SIGNED(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; AgtB ARCHITECTURE Behavior OF compare IS AeqB <= '' WHEN A = B '' ; AgtB <= '' WHEN A > B '' ; AltB <= '' WHEN A < B '' ; Figure 6.26 A our-bit comparator circuit Figure 6.35 A our-bit comparator uing igned number : OUT STD_LOGIC ) ; PROCESS ( w, w, ) IF = '' THEN <= w ; <= w ; : OUT STD_LOGIC ) ; PROCESS ( w, w, ) <= w ; IF = '' THEN <= w ; Figure 6.38 A 2-to- multipleer peciied uing an i-then-ele tatement Figure 6.39 Alternative code or a 2-to- multipleer
5 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; PROCESS ( w ) IF w(3) = '' THEN y <= "" ; ELSIF w(2) = '' THEN y <= "" ; ELSIF w() = '' THEN y <= "" ; y <= "" ; z <= '' WHEN w = "" '' ; Figure 6.4 A priority encoder peciied uing i-then-ele PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; PROCESS ( w ) y <= "" ; IF w() = '' THEN y <= "" ; IF w(2) = '' THEN y <= "" ; IF w(3) = '' THEN y <= "" ; z <= '' ; IF w = "" THEN z <= '' ; Figure 6.4 Alternative code or the priority encoder ENTITY compare IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS PROCESS ( A, B ) AeqB <= '' ; IF A = B THEN AeqB <= '' ; : OUT STD_LOGIC ) ; PROCESS ( w, w, ) CASE IS WHEN '' => <= w ; WHEN OTHERS => <= w ; Figure 6.42 Code or a one-bit equality comparator Figure 6.45 A CASE tatement that repreent a 2-to- multipleer ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS PROCESS ( w, En ) IF En = '' THEN CASE w IS WHEN "" => y <= "" ; WHEN "" => y <= "" ; WHEN "" => y <= "" ; WHEN OTHERS => y <= "" ; y <= "" ; Figure 6.46 A 2-to-4 binary decoder ENTITY eg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; led : OUT STD_LOGIC_VECTOR( TO 7) ) ; END eg7 ; ARCHITECTURE Behavior OF eg7 IS PROCESS ( bcd ) CASE bcd IS -- abcdeg WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN OTHERS => led <= " " ; Figure 6.47 A BCD-to-7-egment decoder
Experiment 4 Decoder Encoder Design using VHDL
Objective: Experiment 4 Decoder Encoder Design using VHDL To learn how to write VHDL code To Learn how to do functional simulation To do study of the synthesis done by VHDL and the theoretical desin obtained
Problem Set 6 Solutions
CS/EE 260 Digital Computers: Organization and Logical Design Problem Set 6 Solutions Jon Turner Quiz on 2/21/02 1. The logic diagram at left below shows a 5 bit ripple-carry decrement circuit. Draw a logic
DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates.
DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS AIM To design and implement encoders and decoders using logic gates. COMPONENTS REQUIRED S.No Components Specification Quantity 1. Digital IC Trainer
Assignment # 3 - CSI 2111(Solutions)
Assignment # 3 - CSI 2111(Solutions) Q1. Realize, using a suitable PLA, the following functions : [10 marks] f 1 (x,y,z) = Σm(0,1,5,7) f 2 (x,y,z) = Σm(2,5,6) f 3 (x,y,z) = Σm(1,4,5,7) f 4 (x,y,z) = Σm(0,3,6)
Shannon decomposition
Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the
Digital Control of Electric Drives
Digital Control of Electric Drives Logic Circuits - equential Description Form, Finite tate Machine (FM) Czech Technical University in Prague Faculty of Electrical Engineering Ver.. J. Zdenek 27 Logic
Shannon decomposition
Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the
ECE223. R eouven Elbaz Office room: DC3576
ECE223 R eouven Elz reouven@uwterloo.c Office room: DC3576 Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) Quiz #1 - Spring 2003 Prof. Anantha Chandrakasan and Prof. Don
COE 328 Final Exam 2008
COE 328 Final Exam 2008 1. Design a comparator that compares a 4 bit number A to a 4 bit number B and gives an Output F=1 if A is not equal B. You must use 2 input LUTs only. 2. Given the following logic
7 Multipliers and their VHDL representation
7 Multipliers and their VHDL representation 7.1 Introduction to arithmetic algorithms If a is a number, then a vector of digits A n 1:0 = [a n 1... a 1 a 0 ] is a numeral representing the number in the
Unit 16 Problem Solutions
5.28 (contd) I. None II. (4, 7)ü (6, 7)ü (2, 4)ü (2, 6)ü Assignment: S =, =, =, =, = A B S Present ate Next ate W = Output S S S Present ate Next ate W = Output T input equations derived from the transition
RAO PAHALD SINGH GROUP OF INSTITUTIONS BALANA(MOHINDER GARH)123029
1 DIGITAL SYSTEM DESIGN LAB (EE-330-F) DIGITAL SYSTEM DESIGN LAB (EE-330-F) LAB MANUAL VI SEMESTER RAO PAHALD SINGH GROUP OF INSTITUTIONS BALANA(MOHINDER GARH)123029 Department Of Electronics & Communication
LECTURE 2: Delay models, std_ulogic and. EECS 316 CAD Computer Aided Design. with-select-when. Chris Papachristou Case Western Reserve University
CAD Computer Aided Design LECTURE 2: Delay models, std_ulogic and with-select-when Instructor: Francis G. Wolff wolff@eecs.cwru.edu Chris Papachristou Case Western Reserve University Review: Full Adder:
ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws
UNIVERSITY OF CALIFORNIA, RIVERSIDE
Final Page of UNIVERITY OF CLIFORNI, RIVERIDE Computer cience Department and Electrical Engineering Department C/EE20 Logic Design Final December, 2000 50 Name: olution Key tudent ID#: Please print legibly
ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University
ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code George Mason University Required reading P. Chu, FPGA Prototyping by VHDL Examples
Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #2 Nov 22, 2006
COE/EE2DI4 Midterm Test #2 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #2 Nov 22, 2006 Instructions: This examination paper includes 12 pages and 20 multiple-choice questions starting
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Decoders and Encoders CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
CHAPTER * 2-2.* Pearson Education Limited Problem Solutions, Global Edition Chapter 2. Verification of DeMorgan s Theorem
HPTER 2 2-.* a) XYZ = X + Y + Z Verification of DeMorgan s Theorem Pearson Education Limited 206. X Y Z XYZ XYZ X + Y + Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b) X + YZ = ( X + Y) ( X + Z) The Second
Table of Content. Chapter 11 Dedicated Microprocessors Page 1 of 25
Chapter 11 Dedicated Microprocessors Page 1 of 25 Table of Content Table of Content... 1 11 Dedicated Microprocessors... 2 11.1 Manual Construction of a Dedicated Microprocessor... 3 11.2 FSM + D Model
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 17 Encoders and Decoders Overview Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can
Pin Details of Digital Logic Gates:
(1) (2) Pin Details of Digital Logic Gates: (3) Postulates and Theorems of Boolean algebra: S. No Postulate/Theorem Duality Remarks 1. X + 0 = X X.1 = X - 2. X + X = 1 X.X = 0-3. X + X = X X.X = X - 4.
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Code Converters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW
Chapter 9. Counters and Shift Registers. Counters and Shift Registers
Chapter 9 Counters and Shift Registers Counters and Shift Registers Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift
Unit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
COMBINATIONAL LOGIC FUNCTIONS
COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present
ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
Preparation of Examination Questions and Exercises: Solutions
Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),
COE 202: Digital Logic Design Combinational Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Combinational Circuits Part 4 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Magnitude comparator Design of 4-bit magnitude comparator
Written exam for IE1204/5 Digital Design with solutions Thursday 29/
Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when
COMBINATIONAL LOGIC CIRCUITS. Dr. Mudathir A. Fagiri
COMBINATIONAL LOGIC CIRCUITS Dr. Mudathir A. Fagiri Standard Combinational Modules Decoder: Decode address Encoder: Encode address Multiplexer (Mux): Select data by address Demultiplexier (DeMux): Direct
Written exam with solutions IE1204/5 Digital Design Friday 13/
Written eam with solutions IE204/5 Digital Design Friday / 207 08.00-2.00 General Information Eaminer: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani
Chapter 3 Combinational Logic Design
Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
Review for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
Luleå Tekniska Universitet Kurskod SMD098 Tentamensdatum
Luleå Tekniska Universitet Kurskod SMD098 Tentamensdatum 991215 Skrivtid 4 timmar Tentamen i Beräkningsstrukturer Antal uppgifter: 6 Max poäng: 30 Betygsgränser: >20 poäng 4 >25 poäng 5 Betygsgränser kan
EXAMINATION in Hardware Description and Verification
Department of VT09 Computer Science and Engineering TDA956/DIT780 Chalmers and Gothenburg University 2009-05-27 EXAMINATION in Hardware Description and Verification DAY : 2009-05-27 TIME : 14:00-18:00
Digital Logic Design ENEE x. Lecture 14
Digital Logic Design ENEE 244-010x Lecture 14 Announcements Homework 6 due today Agenda Last time: Binary Adders and Subtracters (5.1, 5.1.1) Carry Lookahead Adders (5.1.2, 5.1.3) This time: Decimal Adders
Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]
![Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]](/thumbs/81/84077758.jpg "Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]")
Chapter 4: Combinational Logic Solutions to Problems: [, 5, 9, 2, 9, 23, 3, 33] Problem: 4- Consider the combinational circuit shown in Fig. P4-. (a) Derive the Boolean expressions for T through T 4. Evaluate
Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
Combinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
Written reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
control in out in out Figure 1. Binary switch: (a) opened or off; (b) closed or on.
Chapter 2 Digital Circuits Page 1 of 18 2. Digital Circuits Our world is an analog world. Measurements that we make of the physical objects around us are never in discrete units but rather in a continuous
Chapter 3 Combinational Logic Design
Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 1- Implementation Technology and Logic Design Overview Part 1-Implementation Technology and Logic Design Design Concepts
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: EEE QUESTION BANK SUBJECT NAME: DIGITAL LOGIC CIRCUITS SUBJECT CODE: EE55 SEMESTER IV UNIT : Design of Synchronous Sequential Circuits PART
Solutions - Final Exam (Online Section) (Due Date: December 11th by 10:00 am) Clarity is very important! Show your procedure!
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 Solution - Final am (Online Section) (Due Date: December th by : am) Clarity i very important! Show
Slides for Lecture 19
Slides for Lecture 19 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 23 October, 2013 ENEL 353
STEADY CODES WITH HAMMING- DISTANCES 1 AND 2 DGT D = 1 C 2 D = 2 C 1 C Digital Circuits. Hamburg. Prof. Dr. F.
C D = amburg C 2 STEADY CODES C WIT C D = 2 AMMING- DISTANCES AND 2 C 2 C DGT-5 25.3.24 Digital Circuits DECIMA NUMBER 8 WEIGT 4 2 P u P g amburg 2 3 4 5 6 7 8 9 PARITYBIT AT 8-4-2--BCD- CODE DGT-5 25.3.24
ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview
407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation
Written exam with solutions IE Digital Design Friday 21/
Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam
Shannon dekomposition
Shannon dekomposition Claude Shannon matematiker/elektrotekniker 96 William Sandqvist illiam@kth.se ÖH 8.6 Visa hur en 4-to- multipleor kan användas som funktionsgenerator för att te. Generera OR-funktionen.
Function of Combinational Logic ENT263
Function of Combinational Logic ENT263 Chapter Objectives Distinguish between half-adder and full-adder Use BCD-to-7-segment decoders in display systems Apply multiplexer in data selection Use decoders
Chapter # 4: Programmable and Steering Logic
hapter # : Programmable and teering Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. - PLs and PLs Pre-fabricated building block of many N/OR gates (or NOR, NN)
ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference)
ECE 3401 Lecture 23 Pipeline Design Control State Register Combinational Control Logic New/ Modified Control Word ISA: Instruction Specifications (for reference) P C P C + 1 I N F I R M [ P C ] E X 0 PC
Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
Logic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson
Logic Deign CS 270: Mathematical Foundation of Computer Science Jeremy Johnon Logic Deign Objective: To provide an important application of propoitional logic to the deign and implification of logic circuit.
Systems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
Experiment 7: Magnitude comparators
Module: Logic Design Lab Name:... University no:.. Group no: Lab Partner Name: Experiment 7: Magnitude comparators Mr. Mohamed El-Saied Objective: Realization of -bit comparator using logic gates. Realization
Introduction to the Xilinx Spartan-3E
Introduction to the Xilinx Spartan-3E Nash Kaminski Instructor: Dr. Jafar Saniie ECE597 Illinois Institute of Technology Acknowledgment: I acknowledge that all of the work (including figures and code)
CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits
CSEE 3827: Fundamentals of Computer Systems Combinational Circuits Outline (M&K 3., 3.3, 3.6-3.9, 4.-4.2, 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder
Sequential Circuits. CS/EE 3700 : Fundamentals of Digital System Design
Sequential Circuits CS/EE 37 : Fundamentals of igital System esign Chris J. Myers Lecture 7: Flip-flops, Registers, Counters Chapter 7 Combinational output depends only on the input. Sequential output
Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table
Lesson Objectives In this lesson, you will learn about What are combinational circuits Design procedure of combinational circuits Examples of combinational circuit design Combinational Circuits Logic circuit
CB2CE, CB4CE, CB8CE, CB16CE
B2E, B4E, B8E, B16E R B2E, B4E, B8E, B16E 2-, 4-, 8-,16-Bit ascadable Binary ounters with lock Enable and Asynchronous lear Architectures Supported B2E, B4E, B8E, B16E Spartan-II, Spartan-IIE Spartan-3
Written exam with solutions IE1204/5 Digital Design Monday 23/
Written exam with solutions IE204/5 Digital Design Monday 23/0 207 4.00-8.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist Exam text has to be returned when you hand in your
211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.
XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special
Vidyalankar. S.E. Sem. III [EXTC] Digital System Design. Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form
![Vidyalankar. S.E. Sem. III [EXTC] Digital System Design. Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form](/thumbs/96/126594189.jpg "Vidyalankar. S.E. Sem. III [EXTC] Digital System Design. Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form")
S.E. Sem. III [EXTC] Digital System Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form [5] (i) (42) 10 (ii) (17)
Logic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
CSCI 220: Computer Architecture-I Instructor: Pranava K. Jha. BCD Codes
CSCI 220: Computer Architecture-I Instructor: Pranava K. Jha BCD Codes Q. Give representation of the decimal number 853 in each of the following codes. (a) 8421 code (c) 84(-2)(-1) code (b) Excess-three
LOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
Combinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
And Inverter Graphs. and and nand. inverter or nor xor
And Inverter Graphs and and nand inverter or nor xor And Inverter Graphs A B gate 1 u gate 4 X C w gate 3 v gate 2 gate 5 Y A u B X w Y C v And Inverter Graphs Can represent any Boolean function: v i+1
CSE 140 Lecture 11 Standard Combinational Modules. CK Cheng and Diba Mirza CSE Dept. UC San Diego
CSE 4 Lecture Standard Combinational Modules CK Cheng and Diba Mirza CSE Dept. UC San Diego Part III - Standard Combinational Modules (Harris: 2.8, 5) Signal Transport Decoder: Decode address Encoder:
COMBINATIONAL CIRCUITS
OMINTIONL IRUITS pplications Parity Generation and heking Even Parity P e P e P P P P P P5 P P6 ( ) = m(,, ) =, Odd Parity P o P e Three-bit Parity Generator ( ) = m(,,5, ) P P P P P P5 P P6 = 6 Three-bit
A B OUT_0 OUT_1 OUT_2 OUT_
A B OUT_0 OUT_1 OUT_2 OUT_3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 A Decoder is something that does the opposite of encoding; it converts the data back into its original form. This decoder converts
MODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
Logic Design Combinational Circuits. Digital Computer Design
Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional
CS 226: Digital Logic Design
CS 226: Digital Logic Design 0 1 1 I S 0 1 0 S Department of Computer Science and Engineering, Indian Institute of Technology Bombay. 1 of 29 Objectives In this lecture we will introduce: 1. Logic functions
Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
University of Toronto Faculty of Applied Science and Engineering Final Examination
University of Toronto Faculty of Applied Science and Engineering Final Examination ECE 24S - Digital Systems Examiner: Belinda Wang, Jianwen Zhu 2: - 4:3pm, April 26th, 24 Duration: 5 minutes (2.5 hours)
Section 1A. Introduction & Basic Principles. Engineering Areas
ection 1 Introduction & asic Principles Engineering Measurements Engineering reas Research & Development Process Control Fabrication Manufacturing ervice & Maintenance Engineering Measurements 1 2 Engineering
Combinatorial RTL Components
Principles Of Digital Design Combinatorial RTL Components Computation and Reorganization Arithmetic and Comparison Components Logic Components election Components ncoding/decoding Components Bit manipulation
Chapter 9. Counters and Shift Registers. Counters and Shift Registers
Chapter 9 Counters and Shift Registers Counters and Shift Registers Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift
Learning Objectives 10/7/2010. CE 411 Digital System Design. Fundamental of Logic Design. Review the basic concepts of logic circuits. Dr.
/7/ CE 4 Digital ystem Design Dr. Arshad Aziz Fundamental of ogic Design earning Objectives Review the basic concepts of logic circuits Variables and functions Boolean algebra Minterms and materms ogic
Chapter 9. Counters and Shift Registers. Counters and Shift Registers. Counter Terminology 1. Counter Terminology 2. Counter Modulus.
Chapter 9 Counters and Shift Registers Counters and Shift Registers Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift
Chapter 3 Ctd: Combinational Functions and Circuits
Chapter 3 Ctd: Combinational Functions and Circuits 1 Value Fixing, Transferring, and Inverting Four different functions are possible as a function of single Boolean variable Transferring Inverting Value
CSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
Review: Additional Boolean operations
Review: Additional Boolean operations Operation: NAND (NOT-AND) NOR (NOT-OR) XOR (exclusive OR) Expressions: (xy) = x + y (x + y) = x y x y = x y + xy Truth table: x y (xy) x y (x+y) x y x y 0 0 1 0 1
Digital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta
Digital System Design Combinational Logic Assoc. Prof. Pradondet Nilagupta pom@ku.ac.th Acknowledgement This lecture note is modified from Engin112: Digital Design by Prof. Maciej Ciesielski, Prof. Tilman
3. Combinational Circuit Design
CSEE 3827: Fundamentals of Computer Systems, Spring 2 3. Combinational Circuit Design Prof. Martha Kim (martha@cs.columbia.edu) Web: http://www.cs.columbia.edu/~martha/courses/3827/sp/ Outline (H&H 2.8,
CHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
Errata for Fundamentals of Logic Design, 5th ed, hardcover (1st printing)
Errata for Fundamentals of Logic Design, 5th ed, hardcover (1st printing) Look on the back of the title page of the textbook (the copyright page) and you will find a line that reads either 3 4 5 6 7 06
Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu
Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0 s = sum c out carry-out a, b = added bits C = carry in a
Design of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS
CHAPTR VI- CHAPTR VI CHAPTR VI BUILDING BLOCKS R.M. Dansereau; v.. CHAPTR VI- COMBINAT. LOGIC INTRODUCTION -INTRODUCTION Combinational logic Output at any time is determined completely by the current input.
Project Two RISC Processor Implementation ECE 485
Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor
Hardware Implementation of Canonic Signed Digit Recoding
IOSR Journal of VLSI and Signal Proceing (IOSR-JVSP) Volume 6, Iue 2, Ver. I (Mar. -Apr. 2016), PP 11-15 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iorjournal.org Hardware Implementation of Canonic