UNIVERSITY OF CALIFORNIA, RIVERSIDE

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1 Final Page of UNIVERITY OF CLIFORNI, RIVERIDE Computer cience Department and Electrical Engineering Department C/EE20 Logic Design Final December, Name: olution Key tudent ID#: Please print legibly Lab ection: 2 (MW -2): 22 (MW 5-9): 23 (TR 2-5): 24 (TR 6-9): (Numbers in parenthesis denote total possible points for question.). What is the main difference between combinational logic and sequential logic? (2) Combinational components: their output values are computed entirely from their present input values. equential components: their output values are computed using both the present and past input values. 2. What is a duty cycle? (2) Duty cycle is the ratio of clock width and clock period. or the percentage of time that the clock signal is at its asserted level.

2 Final Page 2 of 3. What is a dynamic hazard? (2) dynamic hazard is the possibility of an output changing more than once as the result of a single input transition. 4. Draw the circuit for the bistable element. (2) Q Q' 5. Perform the following calculation in 8-bit binary arithmetic: (2)

3 Final Page 3 of 6. Use oolean algebra to show that the expression (+) () is equivalent to +. (4) (+) ( ) = (+) ( + ) = = +

4 Final Page 4 of 7. Implement a 4-to-2 priority encoder using only 2-input ND, 2-input OR, and NOT gates. (4) The truth table for the 4-to-2 priority encoder is shown on the right. The K-map is shown below. The labels for the entries are ( 0 ny) D D D 3 D 2 D 3 D 2 D D 0 0 ny = D 3 + D 2 0 = D 3 + D 2 'D ny = D 3 + D 2 + D + D 0 D 3 D 2 D D 0 0 ny

5 Final Page 5 of 8. Design the circuit for the E and the LE of an LU that can perform the functions subtract, passthrough, and XOR. The circuits must be simplified. The function passthrough simply passes the value of the first operand to the output. You do not need to draw out the entire LU. (8) 4 points for the E and 4 points for the LE. E M 0 Function Function X Y c 0 Name 0 ubtract + + Pass through all 0 s 0 Functional table 0 b i M 0 b i y i Truth table y i = M 0 b i M E y i LE chematic diagram M 0 Function Function X Y Name 0 0 XOR XOR XOR 0 x Pass through 0 Functional table M a i b i x i = M ( ) + M LE chematic diagram x i

6 Final Page 6 of 9. Using a 5-bit even parity Hamming code, a receiver receives the code What is the 5-bit code that was sent? (4) it positions Parity group for parity bit 8 : Parity group for parity bit 4 : Parity group for parity bit 2 : Parity group for parity bit ; 8+4+2=4 Parity bits it 4 is wrong, thus the code sent was

7 Final Page 7 of 0. Use a PL to implement the function F = w x y + xy z + w xy z + w xyz + wx y + wxy z (4) There are 9 -minterms for F, and only 7 (6-9) 0-minterms for F. The PL is not big enough to implement 9 minterms so we have to implement F and then inverse the output. w x 3 2 y z 0 OR array ND array output array 0 f 3 f 2 f f 0 F

8 Final Page 8 of. Describe the function of the following CMO circuit using a truth table. (4) Give full credit for either one of the following 2 answers. XNOR for this circuit connection OR 0 0 Z Z 0 for this circuit NO connection

9 Final Page 9 of 2. Design a 2-input mux using CMO transistors. (4) Full credit for either one of the following: or 3 points for the following circuit: ND OR ND This is the CMO version of

10 Final Page 0 of 3. Write a structural VHDL program for the 2-input mux. The port signals for the entity is port (,, : in TD_LOGIC; Z: out TD_LOGIC); (4) Only the architecture is needed for full credit. 2 points if it is written as a behavioral code. library IEEE; use IEEE.std_logic_64.all; entity mux is port (,, : in TD_LOGIC; Z: out TD_LOGIC); end mux; architecture mux_gate_arch of mux is signal N, N, : TD_LOGIC; begin U: INV(, N); U2: ND2(, N, N); U3: ND2(,, ); U4: OR2(N,, Z); end mux_gate_arch;

11 Final Page of 4. Eliminate the static hazard in the circuit that implements the function F = y z +wz+w x y. You can just write your solution as a function. (4) yz 00 0 wx 0 yz 00 0 wx With hazard Without hazard F = y z +wz+w x y+wy +x yz+w x z

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws