Fundamentals of Computer Systems
|
|
- Beryl Willis
- 5 years ago
- Views:
Transcription
1 Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25
2 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided 8.5 sheet of your own notes Anything discussed in class is fair game Much like homework assignments Problems will range from easy to difficult; do the easy ones first.
3 Boolean Logic Axioms and Simplification Implicants, Minterms, etc. De Morgan s Theorem Karnaugh Maps Combinational Logic Decoders Multiplexers Timing and Glitches Adders Sequential Logic Bistables; SR Latch; D Latch D Flip-Flops Synchronous Digital Logic Shift Registers Counters Finite State Machines Moore and Mealy Machines The Snail Example The TLC: One-Hot Encoding CMOS Logic Gates The Inverter The CMOS NAND Gate The CMOS NOR Gate A CMOS AND-OR-INVERT Gate General Static CMOS Gates Memories ROMs, EPROMs, and FLASH The SRAM Cell Dynamic RAM Cell PLAs and FPGAs
4 MIPS Architecture/Assembly programming Computational, Load/Store, & Control-flow Instrs. Instruction Encoding Pseudoinstructions Higher-level constructs; subroutines and recursion MIPS Microarchitecture/Datapaths Single-Cycle The datapath for lw, sw, R-type, and branch The controller: instruction decoding Processor Performance Multi-cycle Constructing the datapath The FSM controller Performance Analysis Pipelined Basic pipelined datapath and control Hazards: forwarding, stalling, and flushing Performance Analysis
5 The Memory Hierarchy: Caches Memory hierarchy to make it fast & cheap Temporal and Spatial Locality Memory performance; hit rate Direct-mapped caches n-way set associative caches Fully associative caches
6 The Axioms of (Any) Boolean Algebra A Boolean Algebra consists of A set of values A An and operator An or operator A not operator A false value A A true value A Axioms a b = b a a b = b a a (b c) = (a b) c a (b c) = (a b) c a (a b) = a a (a b) = a a (b c) = (a b) (a c) a (b c) = (a b) (a c) a a = a a = We will use the first non-trivial Boolean Algebra: A = {, }. This adds the law of excluded middle: if a then a = and if a then a =.
7 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms x ( ( x) y ) a b = b a a b = b a a (b c) = (a b) c a (b c) = (a b) c a (a b) = a a (a b) = a a (b c) = (a b) (a c) a (b c) = (a b) (a c) a a = a a = Lemma: x = x (x x) = x (x y) if y = x = x
8 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms x ( ( x) y ) = ( x ( x) ) (x y) a b = b a a b = b a a (b c) = (a b) c a (b c) = (a b) c a (a b) = a a (a b) = a a (b c) = (a b) (a c) a (b c) = (a b) (a c) a a = a a = Lemma: x = x (x x) = x (x y) if y = x = x
9 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms x ( ( x) y ) = ( x ( x) ) (x y) = (x y) a b = b a a b = b a a (b c) = (a b) c a (b c) = (a b) c a (a b) = a a (a b) = a a (b c) = (a b) (a c) a (b c) = (a b) (a c) a a = a a = Lemma: x = x (x x) = x (x y) if y = x = x
10 Simplifying a Boolean Expression You are a New Yorker if you were born in New York or were not born in New York and lived here ten years. Axioms x ( ( x) y ) = ( x ( x) ) (x y) = (x y) = x y Lemma: a b = b a a b = b a a (b c) = (a b) c a (b c) = (a b) c a (a b) = a a (a b) = a a (b c) = (a b) (a c) a (b c) = (a b) (a c) a a = a a = x = x (x x) = x (x y) if y = x = x
11 Alternate Notations for Boolean Logic Operator Math Engineer Schematic Copy x X X or X X Complement x X X X AND x y XY or X Y X Y XY OR x y X + Y X Y X + Y
12 Definitions Literal: a Boolean variable or its complement E.g., X X Y Y Implicant: A product of literals E.g., X XY XYZ Minterm: An implicant with each variable once E.g., XYZ XYZ X YZ Maxterm: A sum of literals with each variable once E.g., X + Y + Z X + Y + Z X + Y + Z
13 Sum-of-minterms and Product-of-maxterms Two mechanical ways to translate a function s truth table into an expression: X Y Minterm Maxterm F X Y X + Y X Y X + Y X Y X + Y X Y X + Y The sum of the minterms where the function is : F = X Y + X Y The product of the maxterms where the function is : F = (X + Y)(X + Y)
14 Minterms and Maxterms: Another Example The minterm and maxterm representation of functions may look very different: X Y Minterm Maxterm F X Y X + Y X Y X + Y X Y X + Y X Y X + Y The sum of the minterms where the function is : F = X Y + X Y + X Y The product of the maxterms where the function is : F = X + Y
15 The Menagerie of Gates Buffer Inverter AND NAND OR NOR XOR XNOR + +
16 De Morgan s Theorem (a b) = ( a) ( b) (a b) = ( a) ( b) AB = A + B = A + B = A B =
17 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W The Karnaugh Map Sum-of-Products Challenge Cover all the s and none of the s using as few literals (gate inputs) as possible. Few, large rectangles are good. Covering X s is optional.
18 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W The minterm solution: cover each with a single implicant. a = W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z 8 4 = 32 literals 4 inv + 8 AND4 + OR8
19 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y Merging implicants helps Recall the distributive law: AB + AC = A(B + C) W a = W X Y Z + W Y + W X Z + W X Y = 2 literals 4 inv + AND4 + 2 AND3 + AND2 + OR4
20 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W Missed one: Remember this is actually a torus. a = X Y Z + W Y + W X Z + W X Y = literals 4 inv + 3 AND3 + AND2 + OR4
21 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W Taking don t-cares into account, we can enlarge two implicants: a = X Z + W Y + W X Z + W X = 9 literals 3 inv + AND3 + 3 AND2 + OR4
22 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W Can also compute the complement of the function and invert the result. Covering the s instead of the s: a = W X Y Z + X Y Z + W Y = 9 literals 5 inv + AND4 + AND3 + AND2 + OR3
23 Karnaugh Map for Seg. a W X Y Z a X X X X X X Z X X X X X Y W To display the score, PONG used a TTL chip with this solution in it: (3) (2) OUTPUT a OUTPUT b
24 Decoders Input: n-bit binary number Output: -of-2 n one-hot code 2-to-4 in out 3-to-8 decoder in out in 4-to-6 decoder out
25 The to-8 Decoder 5 Y A 4 Y Select Inputs B 2 3 Y2 C 3 2 Y3 Y4 Data Outputs Y5 G 6 9 Y6 Enable Inputs G2A 4 7 Y7 G2B 5
26 General n-bit Decoders Implementing a function with a decoder: Every minterm E.g., F = AC + BC I n. I 2 I I n I 2 I I n I 2 I. I n I 2 I I n I 2 I I n I 2 I I n I 2 I C B A F C B A F
27 The Two-Input Multiplexer B A S Y S B A Y B A S S A B Y S B A Y X X X X S Y A B
28 The Four-Input Mux D C B A 3 2 Y D C S 2 S B Y S 2 S Y A B C D A S 2 S
29 General 2 n -input muxes I 2 n. I I 2 n S n S 2 S Y I 2 n I. Y Y = I S n S 2 S + I S n S 2 S + I 2 S n S 2 S +. I 2 n 2S n S 2 S + I 2 n S n S 2 S I 2 n n-to-2 n decoder S n S 2 S
30 Using a Mux to Implement an Arbitrary Function F = AC + BC C B A F
31 Using a Mux to Implement an Arbitrary Function F = AC + BC Apply each value in the truth table: C B A F C B A F
32 Using a Mux to Implement an Arbitrary Function F = AC + BC Apply each value in the truth table: C B A F C B A F
33 Using a Mux to Implement an Arbitrary Function F = AC + BC Apply each value in the truth table: C B A F C B A F
34 Using a Mux to Implement an Arbitrary Function F = AC + BC C B A F
35 Using a Mux to Implement an Arbitrary Function F = AC + BC C B A F
36 Using a Mux to Implement an Arbitrary Function F = AC + BC Can always remove a select and feed in,, S, or S. C B A F C B F A A 3 2 C B Y
37 Using a Mux to Implement an Arbitrary Function F = AC + BC Can always remove a select and feed in,, S, or S. C B A F C B F A A A A 3 2 C B Y
38 Using a Mux to Implement an Arbitrary Function F = AC + BC Can always remove a select and feed in,, S, or S. C B A F C B F A A A A 3 2 C B Y
39 Using a Mux to Implement an Arbitrary Function F = AC + BC Can always remove a select and feed in,, S, or S. C B A F C B F A A A A 3 2 C B Y
40 Using a Mux to Implement an Arbitrary Function F = AC + BC Can always remove a select and feed in,, S, or S. C B A F C B F A A B B In this case, the function just happens to be a mux: (not always the case!) A A 3 2 C B Y B A Y C
41 The Simplest Timing Model In Out t p Each gate has its own propagation delay t p. When an input changes, any changing outputs do so after t p. Wire delay is zero.
42 A More Realistic Timing Model In Out t p(max) t p(min) It is difficult to manufacture two gates with the same delay; better to treat delay as a range. Each gate has a minimum and maximum propagation delay t p(min) and t p(max). Outputs may start changing after t p(min) and stablize no later than t p(min).
43 Critical Paths and Short Paths A B C D Y How slow can this be?
44 Critical Paths and Short Paths A B C D Y How slow can this be? The critical path has the longest possible delay. t p(max) = t p(max, AND) + t p(max, OR) + t p(max, AND)
45 Critical Paths and Short Paths A B C D Y How fast can this be? The shortest path has the least possible delay. t p(min) = t p(min, AND)
46 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A C B B A B BC A B + BC A B + BC C A
47 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A C B B A B BC A B + BC A B + BC C A
48 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A C B B A B BC A B + BC A B + BC C A
49 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A C B B A B BC A B + BC A B + BC C A
50 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A C B B A B BC A B + BC A B + BC C A
51 Glitches A glitch is when a single input change can cause multiple output changes. B A B C A B + BC + AC C A Adding such redundancy only works for single input changes; glitches may be unavoidable when multiple inputs change.
52 Arithmetic: Addition Adding two one-bit numbers: A and B Produces a two-bit result: A B C S C S Half Adder (carry and sum) A B C S
53 Full Adder In general, you need to add three bits: C o + + = + + = + + = + + = + + = + + = C i A B C o S C i A B C i A B C o S S
54 A Four-Bit Ripple-Carry Adder A B A 3 B 3 A 2 B 2 A B A B C o FA C i FA FA FA FA S S 4 S 3 S 2 S S
55 A Two s Complement Adder/Subtractor To subtract B from A, add A and B. Neat trick: carry in takes care of the + operation. B 3 A 3 B 2 A 2 B A B A SUBTRACT/ADD FA FA FA FA S 4 S 3 S 2 S S
56 Overflow in Two s-complement Representation When is the result too positive or too negative?
57 Overflow in Two s-complement Representation When is the result too positive or too negative? % + % + The result does not fit when the top two carry bits differ. A n Bn A n B n S n S n % Overflow
58 Ripple-Carry Adders are Slow A3 B3 A2 B2 A B A B C C4 S3 S2 S S The depth of a circuit is the number of gates on a critical path. This four-bit adder has a depth of 8. n-bit ripple-carry adders have a depth of 2n.
59 Carry Generate and Propagate The carry chain is the slow part of an adder; carry-lookahead adders reduce its depth using the following trick: C A B K-map for the carry-out function of a full adder For bit i, C i+ = A i B i + A i C i + B i C i = A i B i + C i (A i + B i ) = G i + C i P i Generate G i = A i B i sets carry-out regardless of carry-in. Propagate P i = A i + B i copies carry-in to carry-out.
60 Carry Lookahead Adder Expand the carry functions into sum-of-products form: C i+ = G i + C i P i C = G + C P C 2 = G + C P = G + (G + C P )P = G + G P + C P P C 3 = G 2 + C 2 P 2 = G 2 + (G + G P + C P P )P 2 = G 2 + G P 2 + G P P 2 + C P P P 2 C 4 = G 3 + C 3 P 3 = G 3 + (G 2 + G P 2 + G P P 2 + C P P P 2 )P 3 = G 3 + G 2 P 3 + G P 2 P 3 + G P P 2 P 3 + C P P P 2 P 3
61 Bistable Elements Equivalent circuits; right is more traditional. Two stable states:
62 SR Latch R S S R
63 SR Latch R S S R R S Set
64 SR Latch R S S R R S Hold, State
65 SR Latch R S S R R S Reset
66 SR Latch R S S R R S Hold, State
67 SR Latch R S S R R S Huh?
68 SR Latch R S S R R S Set
69 SR Latch R S S R R S Hold, State
70 SR Latch R S S R R S Huh?
71 SR Latch R X S R S X R S Undefined
72 D Latch D C D C inputs outputs C D X
73 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque
74 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque
75 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque opaque transparent
76 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque opaque transparent
77 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque transparent opaque transparent opaque
78 Positive-Edge-Triggered D Flip-Flop D C M Master D C Slave D D D C S C C C D C M D C S transparent opaque transparent opaque opaque transparent opaque transparent
79 D Flip-Flop with Enable D D E C C E D X X X X X D E C What s wrong with this solution? D
80 Asynchronous Preset/Clear PRE D CLR CLK D PRE CLR
81 The Synchronous Digital Logic Paradigm Gates and D flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE C L Every cyclic path contains at least one flip-flop CLOCK NEXT STATE
82 Timing in Synchronous Circuits D C L CLK t c CLK D t c : Clock period. E.g., ns for a MHz clock
83 Timing in Synchronous Circuits D C L CLK Sufficient Hold Time? t p(min,ff) t p(min,cl) CLK D Hold time constraint: how soon after the clock edge can D start changing? Min. FF delay + min. logic delay
84 Timing in Synchronous Circuits D C L CLK t p(max,ff) Sufficient Setup Time? t p(max,cl) CLK D Setup time constraint: when before the clock edge is D guaranteed stable? Max. FF delay + max. logic delay
85 CLK 2 Clock Skew: What Really Happens C L D CLK CLK 2 CLK Sufficient Hold Time? CLK t skew D t p(min,ff) t p(min,cl) CLK 2 arrives late: clock skew reduces hold time
86 CLK 2 Clock Skew: What Really Happens C L D CLK CLK 2 CLK Sufficient Setup Time? CLK t skew D t p(max,ff) t p(max,cl) CLK arrives early: clock skew reduces setup time
87 Cool Sequential Circuits: Shift Registers A 2 3 CLK A 2 3 X X X X X X X X X X
88 Universal Shift Register L 3 2 D 3 2 D D D 3 R S S CLK S S 3 2 R 3 2 D 3 D 2 D D L S S Operation Shift right Load Hold Shift left
89 Cool Sequential Circuits: Counters Cycle through sequences of numbers, e.g.,
90 The 74LS63 Synchronous Binary Counter
91 Moore and Mealy Machines Inputs Next State Logic Next State CLK Current State Output Logic Outputs The Moore Form: Outputs are a function of only the current state.
92 Moore and Mealy Machines Inputs Next State Logic Next State CLK Current State Output Logic Outputs The Mealy Form: Outputs may be a function of both the current state and the inputs. A mnemonic: Moore machines often have more states.
93 Mealy Machines are the Most General Inputs Outputs Current State C L CLK Next State Another, equivalent way of drawing Mealy Machines This is exactly the synchronous digital logic paradigm
94 Moore vs. Mealy FSMs Alyssa P. Hacker has a snail that crawls down a paper tape with s and s on it. The snail smiles whenever the last four digits it has crawled over are. Design Moore and Mealy FSMs of the snail s brain.
95 State Transition Diagrams: Looking for S S S2 S3 S4 Moore Machine: States indicate output / / / / S / S / S2 / S3 / Mealy Machine: Arcs indicate input/output
96 Moore Machine Next State S A S S S S S S S S S2 S2 S3 S2 S2 S3 S S3 S4 S4 S S4 S2 Output S Y S S S2 S3 S4
97 Moore Machine A Next State S A S Output S Y S 2 CLK S 2 Y S CLK S CLK S S
98 Mealy Machine S A S Y S S S S S S S S2 S2 S3 S2 S2 S3 S S3 S
99 Mealy Machine A S A S Y S CLK S CLK Y S S
100 State Transition Diagram for the TLC C + L/T S/T S/T HG H : G F : R FY H : R F : Y Inputs: C: Car sensor S: Short Timeout L: Long Timeout CL/T C + L/T HY H : Y F : R FG H : R F : G S/T S/T C L/T Outputs: T: Timer Reset H: Highway color F: Farm road color S C S L T S HG X X HG HG X X HG HG X HY HY X X HY HY X X FG FG X FG FG X X FY FG X X FY FY X X FY FY X X HG S H F HG G R HY Y R FG R G FY R Y
101 State and Output Encoding S C S L T S HG X X HG HG X X HG HG X HY HY X X HY HY X X FG FG X FG FG X X FY FG X X FY FY X X FY FY X X HG S H F HG G R HY Y R FG R G FY R Y A one-hot encoding: HG HY FG FY G Y R
102 State and Output Encoding S C S L T S X X X X X X X X X X X X X X X X X X S H F T = S CL + S S + S 2 (C + L) + S 3 S S 3 = S 2(C + L) + S 3 S S 2 = S S + S 2 (C + L) S = S CL + S S S = S (CL) + S 3 S H R = S 2 + S 3 H Y = S H G = S F R = S + S F Y = S 3 F G = S 2
103 State and Output Encoding C L S3 FY T = S CL + S S + S 2 (C + L) + S 3 S S 3 = S 2(C + L) + S 3 S HR S 2 = S S + S 2 (C + L) S2 FG S = S CL + S S S = S (CL) + S 3 S H R = S 2 + S 3 S HY H Y = S H G = S FR F R = S + S S S HG F Y = S 3 F G = S 2
104 The CMOS Inverter A Y A 3V p-fet Y n-fet An inverter is built from two MOSFETs: An n-fet connected to ground A p-fet connected to the power supply V
105 The CMOS Inverter A 3V A Y 3V Off V Y On V When the input is near the power supply voltage ( ), the p-fet is turned off; the n-fet is turned on, connecting the output to ground ( ). n-fets are only good at passing s
106 The CMOS Inverter A V A Y 3V On 3V Y Off V When the input is near ground ( ), the p-fet is turned on, connecting the output to the power supply ( ); the n-fet is turned off. p-fets are only good at passing s
107 The CMOS NAND Gate A B Y A Y Two-input NAND gate: two n-fets in series; two p-fets in parallel B
108 The CMOS NAND Gate A B Y A B Y Both inputs : Both p-fets turned on Output pulled high
109 The CMOS NAND Gate A B A B Y Y One input, the other : One p-fet turned on Output pulled high One n-fet turned on, but does not control output
110 The CMOS NAND Gate A B A B Y Y Both inputs : Both n-fets turned on Output pulled low Both p-fets turned off
111 The CMOS NOR Gate A B A B Y Y Two-input NOR gate: two n-fets in parallel; two p-fets in series. Not as fast as the NAND gate because n-fets are faster than p-fets
112 A CMOS AND-OR-INVERT Gate A C Y A B C D Y B D
113 Static CMOS Gate Structure Inputs p-fet pull-up network Y Pull-up and Pull-down networks must be complementary; exactly one should be connected for each input combination. n-fet pull-down network Series connection in one should be parallel in the other
114 Read-Only Memories: Combinational Functions A k. A 2 A A 2 k n ROM D n. D D row column A 6 A 5 A 4 A 3 A 2 A A 28 ROM D General ROM: 2 k words n bits per word Example: Space Race ROM
115 Implementing ROMs / Z: not connected Bitline 2 Bitline Bitline Wordline Wordline A A 2-to-4 Decoder 2 Wordline 2 Add. Data 3 Wordline 3 D 2 D D
116 Implementing ROMs / Z: not connected Bitline 2 Bitline Bitline Wordline Wordline A A 2-to-4 Decoder 2 Wordline 2 Add. Data 3 Wordline 3 D 2 D D
117 Implementing ROMs / Z: not connected A A 2-to-4 Decoder 2 Add. Data 3 D 2 D D
118 Implementing ROMs / Z: not connected A A 2-to-4 Decoder 2 Add. Data 3 D 2 D D
119 CMOS Mask-Programmed ROMs Add. Data ROM programmed by selectively connecting drain wires Active-high wordlines
120 EPROMs and FLASH use Floating-Gate MOSFETs
121 Static Random-Access Memory Cell Bit line Bit line Word line
122 Dynamic RAM Cell Bit line Word line
123 Our Old Pal, the Space Race ROM means and 2 means A3 A2 A A D D D2 D3 D4 D5 D6 D7
124 Our Old Pal, the Space Race ROM The decoder or AND plane In a RAM or ROM, computes every minterm Pattern is not programmable 4 5 A3 A2 A A D D D2 D3 D4 D5 D6 D7
125 Our Old Pal, the Space Race ROM The decoder or OR plane One term for every output Pattern is programmable = the contents of the ROM 4 5 A3 A2 A A D D D2 D3 D4 D5 D6 D7
126 Simplifying the Space Race ROM A A 2 A 3 A Essential minterms mean don t expand these
127 Our New PAL, the Space Race ROM D = 32 D = 32 D 2 = D 3 = D 4 = D 5 = D 6 = D 7 = Saved two ANDs A3 A2 A A D D D2 D3 D4 D5 D6 D7
128 I I I I A (t I/ I/ I/ I/ I/ A 22V PAL: Programmable AND/Fixed OR CLK/I First Fuse Numbers Increments P = 588 R = 589 P = 58 R = 58 P = 582 R = 583 P = 584 R = 585 Macrocell Macrocell Macrocell Macrocell Macrocell P = 586 R =
129 Field-Programmable Gate Arrays (FPGAs) 6 RAM programmable switch LUT LE LE LE Switch Block SB SB LE LE LE Switch Box: 6 programmable switches
Fundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Fall 2011 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables x, y,... represent
More informationUnderstand Video Games; Understand Everything
Understand Video Games; Understand Everything Stephen A. Edwards Columbia University The Subject of this Lecture 0 The Subjects of this Lecture 0 1 But let your communication be, Yea, yea; Nay, nay: for
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2015 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables X,,... represent
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2017 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables,,... represent classes
More informationvidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationFundamentals of Computer Systems
Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012 Encoders and Decoders Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out 00
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationReview for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationCh 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1
Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationLecture 3 Review on Digital Logic (Part 2)
Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal
More informationWritten reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
More informationLecture A: Logic Design and Gates
Lecture A: Logic Design and Gates Syllabus My office hours 9.15-10.35am T,Th or gchoi@ece.tamu.edu 333G WERC Text: Brown and Vranesic Fundamentals of Digital Logic,» Buy it.. Or borrow it» Other book:
More informationFundamentals of Boolean Algebra
UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationALU, Latches and Flip-Flops
CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationWritten exam with solutions IE Digital Design Friday 21/
Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam
More informationCPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic
CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationContents. Chapter 3 Combinational Circuits Page 1 of 36
Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of
More informationEE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
More informationDigital Electronics Sequential Logic
/5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest
More informationReview for B33DV2-Digital Design. Digital Design
Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationBER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO
UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationWritten exam with solutions IE1204/5 Digital Design Monday 23/
Written exam with solutions IE204/5 Digital Design Monday 23/0 207 4.00-8.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist Exam text has to be returned when you hand in your
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
More informationKUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
More informationProblem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction
More informationLecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationChapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More information3 Logic Function Realization with MSI Circuits
3 Logic Function Realization with MSI Circuits Half adder A half-adder is a combinational circuit with two binary inputs (augund and addend bits) and two binary outputs (sum and carry bits). It adds the
More informationAppendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
More informationELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More informationUniversity of Guelph School of Engineering ENG 2410 Digital Design Fall There are 7 questions, answer all questions.
Final Examination Instructor: Shawki M. Areibi Co-examiner: Medhat Moussa. Location: UOG Date: Wednesday, December 5th, 2007 Time: 8:30-10:30 AM Duration: 2 hours. Type: R Closed Book. Instructions: University
More informationReview for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
More informationCS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Logic Design Review Sangyeun Cho Dept. of Computer Science Logic design? Digital hardware is implemented by way of logic design Digital circuits
More information04. What is the Mod number of the counter circuit shown below? Assume initially reset.
. Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / /
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationWritten exam for IE1204/5 Digital Design with solutions Thursday 29/
Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when
More informationFor smaller NRE cost For faster time to market For smaller high-volume manufacturing cost For higher performance
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]
More informationIntroduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationFinal Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90
Final Exam ECE 25, Spring 2008 Thursday, June 12, 2008 Name: PID: Problem Points Score 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 Total 90 1) Number representation (10 pts) a) For each binary vector
More informationDept. of ECE, CIT, Gubbi Page 1
Verification: 1) A.B = A + B 7404 7404 7404 A B A.B A.B 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 A B A B A + B 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 2) A+B = A. B 7404 7404 7404 A B A+B A+B 0 0 0 1 0 1 1 0 1
More informationChapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits
Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic
More informationCSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
More informationAdders allow computers to add numbers 2-bit ripple-carry adder
Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification
More informationSynchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationDigital Design. Sequential Logic
Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary
More informationTopic 8: Sequential Circuits
Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationChapter 5. Digital systems. 5.1 Boolean algebra Negation, conjunction and disjunction
Chapter 5 igital systems digital system is any machine that processes information encoded in the form of digits. Modern digital systems use binary digits, encoded as voltage levels. Two voltage levels,
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationCS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh
CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process
More informationSynchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1
Synchronous Sequential Circuit Design Dr. Ehab A. H. AL-Hialy Page Motivation Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC) Outputs are Function of State (and Inputs)
More informationDIGITAL LOGIC DESIGN
DIGITAL LOGIC DESIGN NUMBERS SYSTEMS AND CODES Any number in one base system can be converted into another base system Types 1) decimal to any base 2) Any base to decimal 3) Any base to Any base Complements
More information