Name. ECE-200 Intelligent Systems

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1 Name Spring 2003 EE-200 Intelligent Systems Pracice Final Solution ll problems have the same weight Problem 1. We are working with a multiplexor that is to switch between four sources (inputs), each one two bits wide. The multiplexor is to have a single active-low enable, and a non-inverting outputs. (a) Tabulate all inputs and outputs of the circuit. Give signal names and short descriptions. D00 through D31: four data sources, each two bits. D00 and D01 are the two bits for source 0, etc. S0, S1: select inputs EN: enable input Y0, Y1: outputs (b) onstruct the truth table. Use the signal names from part (a) EN S1 S0 Y1 Y0 0 x x D01 D D11 D D21 D D31 D30 Problem 2. The equivalence function of two variables is equal to 1 whenever the two variables are equal, and is 0 otherwise. It is sometimes called the XNOR function, and is written as X Y. (a) onstruct a truth table for the equivalence function, and write it as a product of sums. (b) Prove that (X Y) (Y Z) = (X Z). You may use any method you like for the proof. Proof by finite induction. Let F = (X Y) (Y Z), G = X Z X Y Z X Y Y Z F G EE 200 Intelligent Systems Midterm Exam Page 1

2 Problem 3. Given that F(W,X,Y,Z) = S(0,2,8,10,11,13,15). (a)find the prime implicants of this function. The prime implicants are (0,2,8,10) = X Z, (13, 14) = WXZ, (11,15) = WYZ, and (10, 11) = WX Y (b) Find the minimal sum for the function. Two prime implicants are essential: X Z + WXZ. Either of the two remaining prime implicants will complete the function. F = X Z + WXZ + WYZ = X Z + WXZ + WX Y WX YZ Problem 4. ssume that you are constructing a two-level (SOP or POS) circuit for F(W,X,Y,Z) = S(0,2,8,10,11,13,15) consisting of ND, OR gates and inverters. Illustrate on the map a set of product terms that will require the largest number of gates; that is, no other set will need more gates than the configuration you have shown. How many total ND and OR gates are needed? nswer: To have more product terms, we want to have each product term cover fewer cells. The for the greatest number of terms is when we use minterms, which are the 1 s on the map below. There are 7 minterms, so that the circuit uses 7 and gates and one 7 input or gate. WX YZ EE 200 Intelligent Systems Final Exam Page 2

3 Name Problem 5. Implement the parity bit generator, shown in the truth table below, using only an 8:1 multiplexer. Extra redit: Implement the function using only a 4:1 multiplexer. Parity it With an 8:1 multiplexor, we apply,, and at the selection inputs and apply 1 s and 0 s to the appropriate data inputs. For a 4:1 mulitplexor, we apply, to the selection inputs, apply to D0, D3 and to D1, The circuit below uses an 8x1 MUX. V GND EN 74x151 D0 D1 D2 D3 D4 D5 D6 D7 Y Y 5 6 F EE 200 Intelligent Systems Midterm Exam Page 3

4 Problem 6 spy computes the two s complement sum of two binary numbers, then throws the paper into the trash. The I finds the paper, which has gotten smudged so that some of the digits have been erased. Your job is to find the missing digits! Write the answer in the space provided Problem 7. t time t=0 all flip-flops in the circuit shown below are set. D1 D 1 D2 D 2 LOK LK a ) Give the oolean expression for the inputs to the shift register flip-flops. D1 = 2, D2 = 1 2 b) Show the states of the flip-flops in the timing diagram below. Time LK EE 200 Intelligent Systems Final Exam Page 4

5 Name Problem 8 sequential circuit has two inputs ( and ) and contains one D flip-flop that has only D and clock inputs. If = the flip-flop is unchanged, otherwise the flip-flop is complemented. a ) omplete the truth table for a circuit that computes the D input to the flip-flop. Present State and Input D input b ) Write a simple oolean expression for the D input. D = Problem 9. FLSH! Drexel grad, working for INTEL, discovers a new superconducting super-fast switch technology (SSFST). On the way to a better-paying job at UNISYS he informs his employers that his technology can only implement ND gates. Trying to save INTEL, a Drexel coop proposes the following memory circuit. Will this work? onstruct a function table. What name do you recommend for this circuit? D nswer: We write equations for,. =, =D. When either or D are equal to 0, both and are zero. If = D = 1, the = ; =, oth = = 0 and = = 1 are solutions. This circuit has two stable states. However, it cannot be placed into one of them with input signal. This circuit is a FLOP. EE 200 Intelligent Systems Midterm Exam Page 5

6 Problem 10. onstruct state tables, output tables and state diagram for a state-machine that recognizes the occurrence of a particular sequence of bits, regardless of where it occurs in a longer sequence. This sequence-recognizing circuit is to have one input X and one output Z. The circuit is to recognize the occurrence of the sequence of bits 1101 on X by making Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1. Otherwise, Z equals 0. Use no more than 6 states. X X State INIT INIT 0 0 INIT INIT 0 1 Next State Output 0/0 0/0 0/0 INIT 1/0 1/0 1/1 0/0 1/0 EE 200 Intelligent Systems Final Exam Page 6

UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables

UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1