Written exam for IE1204/5 Digital Design with solutions Thursday 29/

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Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander.

1 Written exam for IE4/5 Digital Design with solutions Thursday 9/ General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone Exam text does not have to be returned when you hand in your writing. Aids: No aids are allowed! The exam consists of three parts with a total of 4 tasks, and a total of points: Part A (Analysis) containes ten short questions. Right answer will give you one point. Incorrect answer will give you zero points. The total number of points in Part A is points. To pass the Part A requires at least 6p, if fewer points we will not look at the rest of your exam. Part A (Methods) contains two method problems on a total of points. To pass the exam requires at least points from A + A, if fewer points we will not look at the rest of your exam. Part B (Design problems) contains two design problems of a total of points. Part B is corrected only if there are at least p from the exam A- Part. NOTE! At the end of the exam text there is a submission sheet for Part A, which shall be separated to be submitted together with the solutions for A and B. For a passing grade (E ) requires at least points on the exam. If exactly p from A(6p)+A(4p), (FX), completion to (E) will be offered. Grades are given as follows: F E D C B A The result is expected to be announced before Thursday 9/ 5.

2 Part A: Analysis Only answers are needed in Part A. Write the answers on the submission sheet for Part A, which can be found at the end of the exam text.. p/p A function f(x, y, z) is described by the expression: f ( x, y, z) x y z x y z ( y z) Write down the function maxterms, eg. the function as a product of sums. f ( x, y, z) PoS?. Proposed solution f ( x, y, z) x y z x y z ( y z) ( x y z) xyz yz x y z x z y( z) ( x y z) only one maxterm is needed. p/p A four bit unsigned integer x (xxxx) is to be multiplicated by the constant 7. This is done by connecting the number x to a seven bit adder that is configured to do the operation y = 7x = (8x x) Draw how the adder is to be configured. Except the four bits in x there are also bits with the values and if needed. You will find a copy of the figure on the submission sheet. yz( x ). Proposed solution y 7 x (8 x x). p/p Two binary 6 bit two complement numbers are added. What will the result be expressed as a signed decimal number?. Proposed solution + = = = -7

4. p/p Given is a Karnaugh map for a function of four variables y = f(x, x, x, x). Write the function as a minimized ymin sum of products, SoP form. - in the map means don t care.

p/p A logic function of three variables c b a is realized with multiplexors. Write the function on minimized PoS form (as a product of sums). f ( c, b, a) { PoS} min? 6.

3 4. p/p Given is a Karnaugh map for a function of four variables y = f(x, x, x, x). Write the function as a minimized ymin sum of products, SoP form. - in the map means don t care. 4. Proposed solution y x x x x xxx 5. p/p The figure bellow shows a circuit with two NAND gates and one NOR-gate. Simplify the function Y = f(a, B) as much as possible. 5. Proposed solution Y A A B B A A B B A A B B 6. p/p A logic function of three variables c b a is realized with multiplexors. Write the function on minimized PoS form (as a product of sums). f ( c, b, a) { PoS} min? 6. Proposed solution f ( c, b, a) { SoP} bc abc bc bc abc bc abc ( a a) bc abc abc abc f ( c, b, a) { PoS} min ( b c)( b c)( a c) or ( b c)( b c)( a b)

7. p/p Give an expression for the logical function realized by the CMOS circuit in the figure? Y = f(a,b,c) =? 7. Proposed solution PDN : Y acbc Y Y acbc CMOS Multiplexor 8.

4 7. p/p Give an expression for the logical function realized by the CMOS circuit in the figure? Y = f(a,b,c) =? 7. Proposed solution PDN : Y acbc Y Y acbc CMOS Multiplexor 8. p/p Complete the timing diagram for the D-latch and D-flipflop by drawing signal Q for booth cases. Draw the figure so that it is clear what is causing the changes in the Q! 8. Proposed solution 4

9. p/p The figure shows a synchronous decade counter (QDQCQBQA 9). Mark (= draw in the figure on the answer sheet) the critical path that determines how fast the counter can count.

5 9. p/p The figure shows a synchronous decade counter (QDQCQBQA 9). Mark (= draw in the figure on the answer sheet) the critical path that determines how fast the counter can count. Calculate the minimum time T [ns] between the clock pulses that still provides safe operation. Gates: tpdor = 4, tpdand = 5 [ns] 9. proposed solution Flip-flops: tsu =, th =, tpdq = [ns] T t pdq t psand t psand ns t psor t su. p/p Below is the VHDL code for a : multiplexer. The multiplexer Karnaugh map is shown at right. Complete code so that it becomes a Hazard free MUX. The line of code is also available on the answer sheet. -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_64.all; -- this is the entity entity MUX is port ( a : in std_logic; b : in std_logic; c : in std_logic; Y : out std_logic); end entity MUX; -- this is the architecture architecture gates of MUX is begin Y <= (b AND c) OR (a AND NOT c) end architecture gates;. Proposed solution Y <= (b AND c) OR (a AND NOT c) OR (a AND b); 5

6 Part A: Methods Note! Part A will only be corrected if you have passed part A ( 6p). 5p One older instrument has a seven segment display with seven light bulbs, but it lacks an outlet for connection to a computer. One could therefore need a combinatorial circuit that connects to the bulbs and then converts 7-segment code to the usual BCD code (normal binary coded digits to 9) that is used by a variety of other equipments. a) (p) Set up the truth table for the ten BCD numbers. Black segment is in figure. ( x ) xxx BCD f ( abcdefg) b) (p) Inspect the truth table. You can discover that even if up to two of the segments are excluded as inputs, the relationship remains distinct between image segments and BCD digits. Find one/two segments that you can do without? Derive the new truth-table without this/these segments. c) (p) Draw the karnaugh maps for the four BCD-code bits and derive the minimized expressions for x x x x in SoP-form. Segment combinations that never occurs should be exploited as don t care. (With the excluded segments in the truth table, the number of variables will be manageable). d) (p) Choose yourself one of the expressions x x x x and realize it using only input NAND gates. (No inverted variables are available). Proposed solution abcdefg x xxx Segment a is necessary distinguish between and 7. Segment e is needed to distinguish between 8 from 9 and 5 from 6. Segments c and d could be excluded without the encoding becoming ambiguous. See the figure. This can be used to simplify the problem down to 5 variables abefg x xxx 6

7 x abfg x b a f g af x a f be x f g ae Example. Bit x :. 5p The figure shows a "self-correcting ring counter" counting the "one hot" sequence qqqq,,,. a) (p) Analyze the sequential circuits in the figure and draw the full state diagram and the full state table. If the counter would start in any other state than any of the four desired "one hot" states, how many clock pulses are required, in the worst case, before the counter has "corrected" this and ends up in the correct sequence? 7

8 b) (p) You can also get the same "one-hot" sequence from a Moore machine with four states, see the state diagram to the right. Derive this sequential circuit with D-flip-flops and optional gates. Use the state encoding from the state diagram. Draw the schematic of the circuit.. Proposed solution q q q q q q q q Q Q q q q q Q Q q q q q q Inspection of table gives: Q Q Q Q Decoding: A Q Q C Q Q q q q qqqd d q q q After at most three clock pulses the one hot sequency will be reached! B Q Q D Q Q 8

9 Part B. Design Problems Note! Part B will only be corrected if you have passed part A+A ( p).. 4p Sequence Detector. Different inputs three in a row. You will design a synchronous sequential circuit, in the form of a positive edge-triggered Moore machine with D flip-flops. The input signals a and b are synchronized with the clock pulses C. The output signal z will be when a and b are different in at least three consecutive clock pulse intervals. For other sequences z must be equal to. a) (p) Derive the circuit state table and draw the state diagram. b) (p) Use the Gray code to encode the states and derive the encoded state table. Derive the minimized expressions for next state and for the output. c) (p) Draw the next state decoder circuit, there is only access to AND, OR, and XOR gates.. Proposed solution z q q 4. 6p Inside pulse detector. An asynchronous sequential circuit "Compares" pulses received on two inputs a and b. The pulse at the b input is always a little shorter than the pulse of a, and there will be at most one b-pulse during the interval a. b-pulses will arrive randomly relative to the a-pulse. (There are no exact simultaneous events). 9

Sequence circuit must indicate the case when b is started (becomes one) after a has started (become one), and b has finished (become ) before a finish (become ).

a) First, set up a proper flow table for the sequence circuit. You don t need from the beginning to care about minimizing the number of states.

Various solutions are possible, there is among them a solution with four states). c) Do a suitable state assignement with an exitation table which gives a circuit that is free of critical race. (Hint.

10 Sequence circuit must indicate the case when b is started (becomes one) after a has started (become one), and b has finished (become ) before a finish (become ). The output z will then be = from b's trailing edge to a's trailing edge. z must be for all other cases. See the figure time diagram illustrating this case. a) First, set up a proper flow table for the sequence circuit. You don t need from the beginning to care about minimizing the number of states. All positions in the table that can not occur should be treated as don t care. b) Simplify the state diagram by combining compatible state. (Hint. Various solutions are possible, there is among them a solution with four states). c) Do a suitable state assignement with an exitation table which gives a circuit that is free of critical race. (Hint. Various solutions are possible, there is a solution with two state variables exploiting unstable transition states and uncritical race). You should also derive hazard free expressions for the next state and an expression for output, and draw the circuits with the use of optional gates.. Proposed solution derive state chart step by step - can not occur, double change in input * has not occurred in any of the possible sequences, then will not occur

11 Remove intersecting lines by inserting transition states to avoid hamming distance. z y y y b Hazard cover Good Luck!

12 Submission sheet for Part A Sheet (remove and hand in together with your answers for part A and part B ) Last name: Given name: Personal code: Sheet: Write down your answers for the questions from Part A ( to ) Question Answer f ( x, y, z) PoS? y = 7x = (8x x) Signed decimal?? = f 5 Y f ( A, B)? 4 x, x, x, x ) SoP? ( min 6 f ( c, b, a) { PoS} min? 7 Y = f(a,b,c) =? 8 9 T [ns] = Y <= (b AND c) OR (a AND NOT c) This table is completed by the examiner!! Part A () Part A () Part B () Total () Poäng 4 Sum Grade

Written reexam with solutions for IE1204/5 Digital Design Monday 14/

Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned