ELEN Electronique numérique

Transcription

1 ELEN Electronique numérique Patricia ROUSSEAUX Année académique

2 CHAPITRE 3 Combinational Logic Circuits ELEN

3 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions and Functional Blocks 1.3 Decoders 1.4 Encoders 1.5 Multiplexers 1.6 Implementing Combinational Functions with Multiplexers 2 Arithmetic Functions 2.1 Binary Adders 2.2 Binary Arithmetic 2.3 Binary Adders-Subtractors 2.4 Overflow 2.5 Binary multiplication 2.6 Other Arithmetic Functions ELEN

4 Arithmetic circuits An arithmetic circuit is a combinational circuit that performs arithmetic operations : addition subtraction multiplication division The operations are performed with binary numbers or decimal numbers in a binary code Apply the rules of arithmetic with binary numbers rules for numbers representation resort to 1 or 2 s complements An arithmetic circuit : operates on binary vectors uses the same subfunction for each bit position is made of the iterative interconnection of basic functional blocks, one for each bit position = iterative array ELEN

5 Adders Functional blocks : Half-Adder : a 2-input, 2-output functional block that performs the addition of the two input bits Full-Adder : a 3-input, 2-output functional block that performs the addition of the three input bits, including a third carry input bit obtained from a previous adder Multiple bit adders : Ripple Carry Adder : an iterative array to perform binary addition Carry Look Ahead Adder : an improved structure with higher speed ELEN

6 Half-Adder A Half-Adder performs the following computations: X Y C S It adds two bits to produce a two-bit sum The sum is expressed as a Sum bit, S and a Carry bit, C 139

7 Half-Adder : Truth table From the truth table, we get the equations : For S S S = = X Y + (X X Y = + Y) (X + X Y) Y X Y C S And for C : C = X Y C = ( ( X Y) ) X Y 140

8 Half-Adder : Five Implementations We can derive the 5 following sets of equations for a half-adder: (a) S = X Y + X Y C = X Y (b) S = (X + Y) (X + Y) C = X Y (c) S = ( C+ X Y) C = X Y (d) S = (X + Y) C C = (X + Y) (e) S = X Y C = X Y (a), (b), and (e) are SOP, POS, and XOR implementations for S. In (c), the C function is used as a term in the AND- NOR implementation of S, and in (d), the C function is used in a POS term for S. 141

9 Half-Adder : Implementations The most common half adder implementation is: S = X Y C = X Y X Y S C (e) A NAND only implementation is: (d) S = (X C = ( + Y) C ) ( X Y) C X C S Y XOR 142

10 Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from previous stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. It performs the following computations For a carry-in Z=0 it is the same as the half-adder For a carry- in Z=1 Z X Y C S Z X Y C S

11 Full-Adder : Truth table From the truth table, we get the equations : S C = X Y Z + X Y Z + X Y Z + = X YZ + X YZ + X Y Z+ After simplification : S X Y Odd function C = = X Y C = G + Z + ( X P Z Y) Z X Y Z X YZ X Y Z X Y Z C S

12 Full-Adder : Implementation S = X Y Z C = G + P Z P G The term G=X Y is carry generate. The term P= X Y is carry propagate 145

13 Binary adders To add multiple operands, bits are grouped into vectors Binary adders operate on vectors, for example : add 4-bit input vectors A(0 : 3) and B(0 : 3) to get a sum vector S(0 : 3) a full adder is used for each bit the carry out of adder i becomes the carry in of adder i +1 ELEN

14 4-bit Ripple Carry Adder A 4-bit Ripple Carry Adder is made from four 1-bit full-adders ELEN

15 Ripple-carry adder delay The carry propagation limits the adder speed Suppose carry out is obtained through a two-level circuit instead of the 3-level XOR-AND-OR = number of gate delays ELEN

16 Ripple-carry adder timing diagram Observe carry propagation Suppose ELEN

17 Carry Look Ahead logic All carries C i, i = 1,,n are computed in parallel from the input data All the sums C i, i = 1,,n are computed in parallel Implementation of the carry look ahead logic through a 2-level circuit Large adders can be obtained by cascading simple adders Speed improvement : 4-bit ripple carry adder : 9 gate delays 4-bit carry look ahead adder : 4 gate delays But more complex combinational logic ELEN

18 Full adder - carry generate, carry propagate S i = P i C i Carry C i+1 obtained from two mechanisms : Carry generate : G i = A i B i C i+1 = G i +C i P i generate carry when both Ai and B i equal 1 Carry propagate : P i = A i B i propagate the carry Ci to next adder if one and only one of the two inputs A i, B i equals 1 ELEN

19 Carry look ahead equations Re-express the carry logic in terms of G and P. For a 4-bit adder : C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 0 C 1 = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0 C 4 = G 3 +P 3 C 3 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 +P 3 P 2 P 1 P 0 C 0 ELEN

20 Carry look ahead adder : final implementation The sum bits are obtained after 4 gate delays. ELEN

21 Larger adders A 16-bit adder is made by combining : a cascade of four 4-bit carry look ahead adders a carry look ahead logic circuit to compute intermediate and final carries It can be shown that gate delay is 8 ELEN

22 Integer representation Example : M = 14, N = 12 Unsigned representation : only positive numbers, M = 1110, N = 1100 n = 4 bits Signed representation : positive and negative numbers, one bit is added to represent the sign : 0 for positive numbers, 1 for negative numbers Sign-and-magnitude : the sign bit + n 1 bits for the magnitude M = N = 11100, n = 5 bits two different representations of zero : +0=00000, -0=10000 Ones complement : strictly positive numbers = sign-and-magnitude representation strictly negative numbers : sign bit : 1 + NOT of all magnitude bits : N = 10011, number represented by the n 1 magnitude bits = 2 n 1 1 N two different representations of zero : +0=00000, -0=11111 Two s complement : positive numbers = sign-and-magnitude representation strictly negative numbers : ones complement of N 1 : N = rule : beginning at the least significant bit, copy all 0 and first 1, complement all remaining bits number represented by the n 1 magnitude bits = 2 n 1 N unique representation of zero : ELEN

23 Adder/Subtractor with unsigned numbers, n bits Addition : Simple addition of positive numbers Possible overflow : if result requires n+1 bits Overflow detection : Cn = 1, carry-out of n-th bit adder Subtraction : M N, M > 0, N > problem if M < N : the result is negative, a borrow appears at the most significant bit if direct binary subtraction is used. Example : M = 8, N = 12, n = 4 bits the result of the direct subtraction is equal to the binary representation of 2 n (N M) this is the 2 s complement of N M (magnitude bits), the magnitude of the final result -4 ELEN

24 Unsigned representation : subtraction with 2 s complements Add the 2 s complement of N to M, this provides M +2 n N : if an end carry 2 n appears, this means M N discard it, M N remains s complement No overflow if no end carry, this means N > M take the 2 s complement of M +2 n N to obtain (N-M) place a - sign to its left s complement s complement ELEN

25 Adder/Subtractor with sign-and-magnitude numbers, n bits Consider the three signs : of the two operands M, N and of the operation (+/0 add, -/1 sub) If the parity of the three signs is 0 : M 0 N 0 + M +N M < 0 N < 0 + M N M 0 N < 0 - M + N M < 0 N 0 - M N If the parity of the three signs is 1 : M < 0 N 0 + M +N M 0 N < 0 + M N M 0 N 0 - M N M < 0 N < 0 - M + N ELEN add the magnitudes 2. check for overflow (a carry out of MSB adder) 3. the sign of the result is the same as M 1. use 2 s complement subtraction on magnitudes 2. if carry out of MSB : magnitude OK sign = sign of M 3. if no carry at MSB : magnitude = 2 s complement of subtraction result sign = complement of sign of M

26 Adder/Subtractor with sign-and-magnitude numbers Examples Parity Magnitude 5 5 Sign Carry No carry + -(-)=+ 9+(-4) -9-(-4) Parity Magnitude 13 5 Sign sign of M Carry - - ELEN

27 Adder/Subtractor with signed 2 s complement numbers Addition : 1. add the numbers including the sign bits 2. discard a possible carry out of the sign bits 3. if the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred : proper detection needed Subtraction : 1. form the 2 s complement of the second operand 2. add with the first operand 3. overflow can also occur if the two operands were of opposite sign Examples : (-4) Overflow ELEN

28 Adder/Subtractor implementation The same circuit is used for addition and subtraction For subtraction, the 2 s complement is formed bu complementing each bit and adding 1 to to the result Selection between addition and subtraction is made by variable S For S = 1, subtraction, the 2 s complement is obtained by using XORs to complement bits and adding 1 with C 0 For S = 0, addition, B is passed through XOR gates unchanged. ELEN

29 2-s complement adder : Overflow detection Overflow occurs if n+1 bits are required to contain the result of an n-bit addition It can only occur if the two operands are of the same sign The result should also be of the same sign It is linked to carries C n and C n 1 who affect the sign bit of the sum C n C n A n B n S n OK KO OK KO The overflow is detected by V = C n C n 1 ELEN

30 Circuit for overflow detection Unsigned adder/subtractor : addition : C = 1, overflow subtraction C = 0, correction step required, compute the 2 s complement of the result Signed 2 s complement adder/subtractor : addition and subtraction : V = 1, overflow ELEN

31 Binary multiplication Same rule as for decimal numbers. Take each bit of the multiplier, starting with the least significant one 1. Multiply the multiplicand by each bit of the multiplier 2. Left shift partial result to obtain a partial product 3. Add all the partial products Step 1 simply amounts to AND the multiplier bit with each bit of the multiplicand Binary adders are used after each partial multiplication to derive a partial product ELEN

32 Binary Multiplication Multiply B and A ELEN

33 Multiplier circuit ELEN

34 Other arithmetic functions The functional blocks already defined can be simplified to implement other elementary functions : incrementing : add a fixed value to an arithmetic variable examples : A+1, B +3 easily obtained by simplifying a ripple carry adder decrementing : subtracting a fixed value multiplication by a constant... Have a look in the reference book ELEN

35 CHAPITRE 4 Sequential circuits ELEN

36 1 Fundamentals of Sequential Circuits 1.1 Motivation 1.2 Synchronous and Asynchronous Circuits 1.3 State, State Diagram and State Table 1.4 Time simulation 2 Latches 3 Flip-Flops 4 State diagrams and State Tables 5 Finite State Machine Diagrams ELEN

37 Sequential versus Combinational Combinational systems are memoryless Outputs depends only on the present inputs Sequential systems have memory The memory is stored in a State Outputs depend on the present and previous inputs There exits a feedback between outputs and inputs ELEN

38 Components of a sequential Circuit A sequential circuit is made of : storage elements : latches and flip-flops a combinational circuit which implements a multiple output switching function Inputs are signals from the outside The Present State gathers output signals from storage elements Outputs are signals to the outside The remaining outputs constitute the Next State and are inputs of the storage elements ELEN

39 Types of Sequential Circuits Two types depending on the times at which storage elements : observe their inputs change their state Asynchronous systems : the behavior is defined from knowledge of inputs at any time instant and the order in which inputs change changes in state occur at any time instant Synchronous systems : the behavior is defined from knowledge of all inputs at the same discrete time instants changes in state occur at these specific discrete times synchronization is achieved by a clock generator producing clock pulses the clock period is the time between state changes ELEN

40 Example of a sequential system Door combination lock Enter 3 numbers in sequence and the door opens If there is an error, the lock must be reset After the door opens, the lock must be reset Inputs : sequence of numbers; reset Outputs : door open/close Memory : the combination of numbers must be remembered ELEN

41 Implement using sequential logic Use synchronous system the clock tells us when to look at inputs : a new number or reset signal Sequential system : memorize the sequence of numbers if an error occurred How to define the states? What is important is the transition from one state to the other, implied by changes in inputs The state transitions are represented on a State Diagram and a State Table The value of the output has to be defined for each state ELEN

42 Example : states We can consider 5 different states : S1 : state after reset, wait for first number, the output is closed S2 : the first correct number has been received, the output is closed S3 : the sequence of 1st and 2nd correct numbers has been received, the output is closed S4 : the sequence of the three correct numbers has been received, the output is open S5 : an incorrect number has been received, this is the error state, output is closed We will need 3 bits to encode the 5 states and thus 3 basic memorizing cells, used in parallel. We will learn latter how to build state diagrams and state tables. ELEN

43 Discrete event simulation In order to test the behavior of a sequential circuit we will have to simulate the time evolution of outputs and states. The propagation delays introduced by the gates present in the circuit have to be taken into account This is done by a discrete event simulation tool which implements the following rules : The gates are modeled by an ideal (instantaneous) function and a fixed gate delay Any change in input values is evaluated to see if it causes a change in output value Changes in output values are imposed after the proper gate delay following the input change The inputs driven by the output are accordingly changed ELEN

44 Example : simulation of a NAND gate ELEN

45 A small combinational circuit ELEN

46 Feedback creates memory - Inclusion of a storing state ELEN

47 Information path if S=1 Two modes of operation : Transparent mode Input is passed to the output ELEN

48 Information path if S=0 Memorizing mode Y remembers the previous input ELEN

49 Timing and gate delays Y is the state of the system The design of the circuit should be done in such a way that gate delays can be neglected with respect to the time period between input changes The duration of storage of a value should be longer than the gate delays We can represent the system time evolution with the following table, showing the successive values of inputs B and S and state Y ELEN

50 Unstable circuit - Oscillator If an inverter is added in the feedback path The circuit becomes unstable This race behavior should most of the time be avoided In this case, for S = 0, the circuit becomes an oscillator The period of oscillation is linked to the gate delays ELEN

51 How to control feedback? Storage can be constructed from logic with delay connected in a closed loop To be stable, there must be no inversion of the signal in the loop Two inverters in cascade form a basic memory cell The value is hold as long as power is applied : Memorizing mode How to get a new value in the memory cell? selectively break the feedback path : transparent mode load the new value into cell ELEN

52 1 Fundamentals of Sequential Circuits 1.1 Motivation 1.2 Synchronous and Asynchronous Circuits 1.3 State, State Diagram and State Table 1.4 Time simulation 2 Latches 3 Flip-Flops 4 State diagrams and State Tables 5 Finite State Machine Diagrams ELEN

53 Real Basic Memory Element (1bit) : the LATCH ( Verrou ) state = 1 binary variable = 1 bit capability to force output to 0 or 1 asynchronous storage elements from basic to more elaborated latches : 1. basic (NOR) SR Latch 2. basic (NAND) S R Latch 3. clocked SR Latches 4. D Latch ELEN

54 Basic SR Latch Formed by 2 cross-coupled NOR gates The states are defined by outputs Q, Q which normally are reciprocally complemented values There are thus 2 useful states : the Set State : Q = 1, Q = 0 the Reset State : Q = 0, Q = 1 There are two inputs : set input S : S = 1 brings the system in its Set state reset input R : R = 1 brings the system in its Reset state ELEN

55 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

56 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

57 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

58 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

59 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

60 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

61 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

62 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

63 SR Latch behavior 1. start with R = 0, S = 0, the stored state is initially unknown 2. S changes to 1, this sets Q to 1 3. S back to 0, Q remembers 1 thus, two input conditions cause the system to be in set state 4. R changes to 1, this resets Q to 0 5. R back to 0, now Q remembers 0 thus, two input conditions cause the system to be in reset state 6. suppose both S and R changes to 1 7. both Q and Q are zero!!!, undefined state 8. if both R and S go to zero simultaneously, can lead to unstable or race condition, oscillating between 00 and 11 undefined states ELEN

64 Timing diagram Race conditions : 1. S = R = 1, Q = 0, Q = 0 2. S and R go simultaneously to gate delay later Q = 1, Q = gate delay later Q = 0, Q = ELEN

65 Timing diagram Race conditions : 1. S = R = 1, Q = 0, Q = 0 2. S and R go simultaneously to gate delay later Q = 1, Q = gate delay later Q = 0, Q = ELEN

66 Timing diagram Race conditions : 1. S = R = 1, Q = 0, Q = 0 2. S and R go simultaneously to gate delay later Q = 1, Q = gate delay later Q = 0, Q = ELEN

67 Timing diagram Race conditions : 1. S = R = 1, Q = 0, Q = 0 2. S and R go simultaneously to gate delay later Q = 1, Q = gate delay later Q = 0, Q = In practice, it is very difficult to observe the SR Latch in the 1-1 state since one S or R usually changes first. The latch ambiguously resturns to state 0-1 or 1-0. ELEN

68 SR Latch state table The time behavior of the SR Latch is summarized in the state table showing next state based on the current inputs (S,R) and the current state Q(t) S R Q(t) Q(t + ) hold previous state reset set X forbidden X It can also be described by the following equation : Q(t + ) = S + RQ(t) is the gate delay, the time between change in input and corresponding change in state. One usually writes Q(t +1). ELEN

69 Basic S R Latch The cross-coupling of 2 NAND gates presents a similar behavior with : S = 0 to switch to set state R = 0 to switch to reset state both R = 0, S = 0 corresponds to an undefined state S R Q(t) Q(t + ) hold previous state reset set X forbidden X Q(t +1) = S +RQ(t) ELEN

70 Controlled SR Latch A control or enable or clock input C is added The state can only change if the control input is low The S, R inputs are only observed when C is low The behavior and the state table are exactly the same as those of the SR Latch (with NOR gates) when C = 1 When C = 0, the state remains unchanged, regardless of the values of S and R The problem of the undefined state remains : C = 1, S = 1, R = 1 ELEN

71 D Latch The undefined state is removed by imposing necessarily different values to inputs S and R To this end, an inverter is added There remains one input D : D = 1 is equivalent to S = 1 D = 0 is equivalent to R = 1 ELEN

72 D latch : modes of operation When C = 0 : the latch is in its memorizing mode, the output is the memorized state When C = 1 : the latch is in its transparent mode, the output follows the input C D Q(t) Q(t + 1) 0 X 0 0 memorizing mode 0 X reset set Q(t +1) = CQ(t)+CD ELEN

73 Références Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime, Course material http ://writphotec.com/mano4/ Cours d électronique numérique, Aurélie Gensbittel, Bertrand Granado, Université Pierre et Marie Curie http ://bertrand.granado.free.fr/licence/ue201/ coursbeameranime.pdf Lecture notes, Course CSE370 - Introduction to Digital Design, Spring 2006, University of Washington, https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/ ELEN

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