WEEK 3.1 MORE ON KARNAUGH MAPS
|
|
- Evan McDowell
- 6 years ago
- Views:
Transcription
1 WEEK 3. MORE ON KARNAUGH MAPS
2 Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather than using a or a, we can use an X to mark a don t care. Why are don t cares important and useful??? Well, if we are looking for a minimum representation using as few literals and gates as possible, we can force the don t care locations to either or, however it helps us. ECE24 Digital Circuits and Systems Page 2
3 Example of Don t Cares Consider the following four input function where there are three input patterns for which the output can be either or, and we don t care which. For the smallest SOP implementation, it appears good to let one of the don t cares be a, while the other 2 are. Question: Is there another equally as good implementation that uses the don t cares differently? ECE24 Digital Circuits and Systems Page 3
4 Logical vs. Algebraic Equivalence When we have don t cares, we can get equally good expressions that are logically correct (i.e., we get output of when it must be, and when it must be ). However, depending on how we use the don t cares, multiple expressions will not equal each other algebraically. Note that both f and f 2 are valid implementations of f, but are not algebraically equal to each other since the don t cares are used differently when finding both f and f 2. ECE24 Digital Circuits and Systems Page 4
5 Multiple Output/Function Minimization Sometimes, we might have multiple functions that require minimization. We can minimize each function individually, but sometimes the overall circuit implementation will be better if we consider both functions simultaneously. Basically, we will try to find common product terms useful for both functions and then share them. ECE24 Digital Circuits and Systems Page 5
6 Example of Multiple Output/Function Minimization Consider the following 2, four input functions and the minimal implementation of each function separately. The functions have no product terms in common. The cost of f_ is OR + 3 AND + gate inputs = 4. The cost of f_2 is OR + 3 AND + gate inputs = 5. Therefore, to implement the entire circuit the cost is 29. ECE24 Digital Circuits and Systems Page 6
7 Example of Multiple Output/Function Minimization Consider trying to include some product terms that appear in both K-Maps. The individual expressions for f and f 2 are not the best, but If we consider that 2 product terms are shared, the entire circuit requires 2 OR + 4 AND + 7 gate inputs. The total cost of the entire circuit is 23. ECE24 Digital Circuits and Systems Page 7
8 Multiple Outputs Illustrated ECE24 Digital Circuits and Systems Page 8
9 Some More Terminology Useful to be aware of some terminology When we have a function and we are told the output is or for every possible input, the function is called completely specified. When we have a function and are told the output is or for only some of the inputs, we can assume the other inputs have don t cares as outputs. It the situation that we have don t care outputs, the function is incompletely specified. Consider the minterms for any function. We can separate the minterms in to three sets: The on-set is those minterms which require the output to be. The off-set is those minterms which require the output to be. The dc-set is those minterms which have an output of X (don t care). ECE24 Digital Circuits and Systems Page 9
10 Implicants, Prime Implicants and Covers A product term is called an Implicant if the logic function outputs a for all minterms in the product term. E.g., all rectangles in a K-Map that contain only s are implicants. An Implicant is called a Prime Implicant if the removal of any literal from the implicant results in a new product term that is not an implicant. E.g., Removing any literal from a product term in a K-Map corresponds to increasing the size (doubling the area) of the rectangle. If we cannot increase the size of the rectangle without including a, then the implicant is prime. A cover is a collection of implicants that account for all cases in which the function is. We can always form a cover using only prime implicants. ECE24 Digital Circuits and Systems Page
11 Example of Implicants In the K-Map, product terms x and x 2 x 3 are prime implicants. Product term x x 2 is an implicant, but it is not a prime implicant. ECE24 Digital Circuits and Systems Page
12 Essential Prime Implicants A prime implicant is called an Essential Prime Implicant if it includes a minterm that in not found in any other prime implicant. In realizing any function using only prime implicants, all essential prime implicants must be included! If not, we would miss terms for which the function outputs a. ECE24 Digital Circuits and Systems Page 2
13 Why all this Terminology? Understanding implicants, primes and essentials help us form a more methodical procedure for minimization of logic functions. Covers using prime implicants typically have low cost. So to minimize, we should Generate prime implicants. Identify essential prime implicants. Include the essential prime implicants in the cover. If the function is covered, stop. Include as few non-essential prime implicants to finish covering the function. And then stop ECE24 Digital Circuits and Systems Page 3
14 Methodical Example The following K-Map has 6 prime implicants. 4 of them are essential, 2 are not essential. ECE24 Digital Circuits and Systems Page 4
15 Supplmentary Notes on KMaps Some people have trouble understanding why the area of the rectangles in the K-map must always double in size when combining boxes, but it important to understand what s happening when you use a K-Map. Understanding K-Maps is important! So, I ll do a simple example here, illustrating what is happening in the K-Map, the truth table and in Boolean Algebra. ECE24 Digital Circuits and Systems Page 5
16 The Example Say we have the following function with 4-inputs. We can draw the truth table, the K-Map, and write the Canonical SOP using minterms. xx2 x3x4 m m4 m2 m8 m m5 m3 m9 m3 m7 m5 m m2 m6 m4 m Note that the minterms are x boxes (area ) in the K-Map. ECE24 Digital Circuits and Systems Page 6
17 The Example (First Step) Rearrange and duplicate rows of the truth table so that pairs of rows adjacent to each other produce an output of. Make sure only variable changes in these pairs of rows. We can put m and m 3 next to each other; We can put m 5 and m 7 next to each other; We can put m 3 and m 5 next to each other; We can put m 6 and m 7 next to each other. ECE24 Digital Circuits and Systems Page 7
18 What Happens Algebraically (First Step)? Since only variable in changing, we can duplicate minterms (which are product terms) and factor out a common part. The result is a set of product terms with some variables removed. ECE24 Digital Circuits and Systems Page 8
19 What Happens In the K-Map (First Step)? In the K-Map, we see that the x boxes grow to be boxes of area 2 (i.e., x2 or 2x). x3x4 xx2 x3x4 xx2 m m4 m2 m8 m m4 m2 m8 m m5 m3 m9 m m5 m3 m9 m3 m7 m5 m m3 m7 m5 m m2 m6 m4 m m2 m6 m4 m The boxes have DOUBLED in size by merging with an adjacent box of compatible dimension. The result are product terms that handles two rows (minterms) in the truth table. ECE24 Digital Circuits and Systems Page 9
20 The Example (Second Step) Again, rearrange and duplicate rows of the condensed truth table so that pairs of rows adjacent to each other produce an output of. Make sure only variable changes in these pairs of rows. If a variable was removed and replaced with - previously, then the - must match too!!! We can put (m,m 3 ) and (m 5,m 7 ) next to each other. (Only x 2 changes and doesn t matter; x 3 = - in both cases). We can put (m 5,m 7 ) and (m 3.m 5) next to each other. (Only x changes and doesn t matter; x 3 = - in both cases). ECE24 Digital Circuits and Systems Page 2
21 What Happens Algebraically (Second Step)? Since only variable in changing, we can duplicate product terms and factor out a common part of the product terms. The result is a set of product terms with some variables removed. ECE24 Digital Circuits and Systems Page 2
22 What Happens In the K-Map (Second Step)? In the K-Map, we see that (some) of the squares of area two have been expanded to be squares of area 4. x3x4 xx2 x3x4 xx2 m m4 m2 m8 m m4 m2 m8 m m5 m3 m9 m m5 m3 m9 m3 m7 m5 m m3 m7 m5 m m2 m6 m4 m m2 m6 m4 m The boxes have DOUBLED in size by merging with an adjacent box of compatible dimension. The result are product terms that handles four rows (minterms) in the truth table. ECE24 Digital Circuits and Systems Page 22
23 The Summary So why do rectangles in the K-Map need to have areas of, 2, 4, 8, etc Given a product term, we need to find another product term involving the same set of variables. For these two product terms, it must also be true that one and only one variable appears in complemented form in one of the product terms and in un-complemented form in the other product term. The two product terms get merged by factoring out the common part which gives something like the following: Therefore, we are always merging pairs (two) of product terms. Since we begin with minterms (area ), and merge, and merge, etc. We should see that areas will always double going, 2, 4, 8, 6, etc ECE24 Digital Circuits and Systems Page 23
24 XOR gates XOR gates are expensive to implement in silicon, but they are very useful for circuits like parity checkers and arithmetic circuits (e.g., adders, subtractors, and so forth). Sometimes, we can find an XOR gate hidden or buried inside of a lot of AND, OR and NOT gates. If we can find and extract the XOR gate, we can take advantage of it to get a large savings in circuit size. Recall truth tables for XOR and NXOR These gates perform the odd and even functions, respectively (with 2-inputs, they perform the difference or equivalence functions, respectively). ECE24 Digital Circuits and Systems Page 24
25 4-input XOR and NXOR truth tables (for illustration purposes) ECE24 Digital Circuits and Systems Page 25
26 XOR and XNOR functions using AND, OR and NOT gates Notice that we can implement XORs using AND, OR and NOT gates: ECE24 Digital Circuits and Systems Page 26
27 K-Maps for 4-Input XOR and XNOR XOR and XNOR gates have checker-board patterns in their K-Maps. xx2 xx2 x3x4 x3x4 ECE24 Digital Circuits and Systems Page 27
28 How can XORs Sometimes Reduce Implementation Size? Sometimes, it might be true that XORs are hidden inside of other logic. By finding and extracting an XOR, we might get a very simple circuit. xx2 x3x4 The first equation above is the minimum Sum-Of-Products 6 AND gates (2, 4-input, 4, 3-input) and OR gate (6 inputs). ECE24 Digital Circuits and Systems Page 28
29 Continuing Our Example xx2 x3x4 ECE24 Digital Circuits and Systems Page 29
30 Finishing Our Example We can draw a circuit We can see what is happening with the XOR by drawing the K-Maps for x, x 2, x 3, x 4 and overlaying them We are taking advantage of the XOR odd property. x3x4 xx2 x3x4 xx2 x3x4 xx2 x3x4 xx2 ECE24 Digital Circuits and Systems Page 3
31 XOR Summary In general, finding and extracting XOR gates is a complicated and hard problem. When we can write a function as the XOR of a bunch of Product Terms (ANDs), we are finding not Sum-Of-Products, but rather Exclusive Sum-Of-Products (ESOP). ECE24 Digital Circuits and Systems Page 3
32 Another XOR Example Just another example of finding an XOR (but not an ESOP) The K-Map appears to have an XOR pattern x3x4 xx2 The input x3 is acting like a gating signal, preventing the XOR from affecting the output when it shouldn t (we can gate signals with ANDs). ECE24 Digital Circuits and Systems Page 32
Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18
University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total
More informationWEEK 2.1 BOOLEAN ALGEBRA
WEEK 2.1 BOOLEAN ALGEBRA 1 Boolean Algebra Boolean algebra was introduced in 1854 by George Boole and in 1938 was shown by C. E. Shannon to be useful for manipulating Boolean logic functions. The postulates
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationUnit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
More informationCombinational Logic Circuits Part II -Theoretical Foundations
Combinational Logic Circuits Part II -Theoretical Foundations Overview Boolean Algebra Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems Boolean Function and Representations
More informationThis form sometimes used in logic circuit, example:
Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from
More information14:332:231 DIGITAL LOGIC DESIGN
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall Lecture #: Combinational Circuit Synthesis II hat if we have input variables? V = V = of Example with variables
More informationThe Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,
More informationXI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.
2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two
More informationWeek-I. Combinational Logic & Circuits
Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and
More informationSimplification of Boolean Functions. Dept. of CSE, IEM, Kolkata
Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,
More informationGate-Level Minimization
Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable
More informationChapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
More informationUNIT 4 MINTERM AND MAXTERM EXPANSIONS
UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and
More informationXOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.
XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special
More informationChapter 4 Optimized Implementation of Logic Functions
Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization
More informationUNIVERSITI TENAGA NASIONAL. College of Information Technology
UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours
More informationMC9211 Computer Organization
MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2015 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables X,,... represent
More informationLogic Design. Chapter 2: Introduction to Logic Circuits
Logic Design Chapter 2: Introduction to Logic Circuits Introduction Logic circuits perform operation on digital signal Digital signal: signal values are restricted to a few discrete values Binary logic
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationCombinational Logic. Review of Combinational Logic 1
Combinational Logic! Switches -> Boolean algebra! Representation of Boolean functions! Logic circuit elements - logic gates! Regular logic structures! Timing behavior of combinational logic! HDLs and combinational
More informationLecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
More informationMidterm1 Review. Jan 24 Armita
Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon
More informationII. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):
ENGI 386 Digital Logic II. COMBINATIONAL LOGIC DESIGN Combinational Logic output of digital system is only dependent on current inputs (i.e., no memory) (a) Boolean Algebra - developed by George Boole
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationDigital Circuit And Logic Design I. Lecture 4
Digital Circuit And Logic Design I Lecture 4 Outline Combinational Logic Design Principles (2) 1. Combinational-circuit minimization 2. Karnaugh maps 3. Quine-McCluskey procedure Panupong Sornkhom, 2005/2
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
More informationL4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES
L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore
More informationCombinational Logic Fundamentals
Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic
More informationLecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
More informationAdditional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND
More information14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all Lecture #: Combinational Circuit Synthesis I Combinational Circuit Synthesis Recall: Combinational circuit
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 2 Following the slides of Dr. Ahmed H. Madian ذو الحجة 438 ه Winter
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More information9/29/2016. Task: Checking for a Lower-Case Letter. ECE 120: Introduction to Computing. Change C 5 to C 5 to Obtain L(C) from U(C)
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 12: Introduction to Computing Multiplexers (Muxes) Task: Checking for a Lower-Case Letter What if we also need
More informationSlide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 3 for ENEL 353 Fall 2016 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2016 SN s ENEL 353 Fall 2016 Slide Set 3 slide
More informationBoolean Algebra and Digital Logic
All modern digital computers are dependent on circuits that implement Boolean functions. We shall discuss two classes of such circuits: Combinational and Sequential. The difference between the two types
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Fall 2011 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables x, y,... represent
More informationCSE 140: Components and Design Techniques for Digital Systems
Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean Algebra
More informationOptimizations and Tradeoffs. Combinational Logic Optimization
Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming
More informationWorking with Combinational Logic. Design example: 2x2-bit multiplier
Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs
More informationPrinciples of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
More informationCS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman
CS 121 Digital Logic Design Chapter 2 Teacher Assistant Hanin Abdulrahman 1 2 Outline 2.2 Basic Definitions 2.3 Axiomatic Definition of Boolean Algebra. 2.4 Basic Theorems and Properties 2.5 Boolean Functions
More informationELC224C. Karnaugh Maps
KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on
More informationDigital Logic Design. Combinational Logic
Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal
More informationChapter 2. Digital Logic Basics
Chapter 2 Digital Logic Basics 1 2 Chapter 2 2 1 Implementation using NND gates: We can write the XOR logical expression B + B using double negation as B+ B = B+B = B B From this logical expression, we
More informationLogic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
More informationCMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps
CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple
More informationCPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter
More informationKarnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2 Boolean Algebra and Logic Gates Basic Definitions A binary operator defined on a set S of elements is a rule that assigns, to each pair of elements from S, a unique element from S. The most common
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic
More informationUNIT 5 KARNAUGH MAPS Spring 2011
UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable
More informationFunctions. Computers take inputs and produce outputs, just like functions in math! Mathematical functions can be expressed in two ways:
Boolean Algebra (1) Functions Computers take inputs and produce outputs, just like functions in math! Mathematical functions can be expressed in two ways: An expression is finite but not unique f(x,y)
More informationfor Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
More informationCMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification
CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization
More informationCSE 140 Midterm I - Solution
CSE 140 Midterm I - Solution 1. Answer the following questions given the logic circuit below. (15 points) a. (5 points) How many CMOS transistors does the given (unsimplified) circuit have. b. (6 points)
More informationKarnaugh Maps Objectives
Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between
More informationENG2410 Digital Design Combinational Logic Circuits
ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single
More informationE&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev
E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean
More informationProve that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).
hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove
More informationTextbook: Digital Design, 3 rd. Edition M. Morris Mano
: 25/5/ P-/70 Tetbook: Digital Design, 3 rd. Edition M. Morris Mano Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 25/5/ P-2/70 Chapter 3 Gate-Level Minimization
More informationCombinatorial Logic Design Principles
Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1 Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages
More informationDigital Logic (2) Boolean Algebra
Digital Logic (2) Boolean Algebra Boolean algebra is the mathematics of digital systems. It was developed in 1850 s by George Boole. We will use Boolean algebra to minimize logic expressions. Karnaugh
More informationBuilding a Computer Adder
Logic Gates are used to translate Boolean logic into circuits. In the abstract it is clear that we can build AND gates that perform the AND function and OR gates that perform the OR function and so on.
More informationLecture 4: Four Input K-Maps
Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems Fall 24 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean
More informationCombinational Logic Design/Circuits
3 ` Combinational Logic Design/Circuits Chapter-3(Hours : 12 Marks:24 ) Combinational Logic design / Circuits 3.1 Simplification of Boolean expression using Boolean algebra. 3.2 Construction of logical
More informationIn Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y. Logic Gate. Truth table
Module 8 In Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y Logic Gate Truth table A B Y 0 0 0 0 1 1 1 0 1 1 1 0 In Module 3, we have learned about
More informationLogic Gate Level. Part 2
Logic Gate Level Part 2 Constructing Boolean expression from First method: write nonparenthesized OR of ANDs Each AND is a 1 in the result column of the truth table Works best for table with relatively
More informationE&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates
Digital Circuits & Systems Lecture Transparencies (Boolean lgebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean lgebra & Logic Gates Major topics Boolean algebra NND & NOR gates Boolean algebra
More informationChapter 2 Boolean Algebra and Logic Gates
Chapter 2 Boolean Algebra and Logic Gates Huntington Postulates 1. (a) Closure w.r.t. +. (b) Closure w.r.t.. 2. (a) Identity element 0 w.r.t. +. x + 0 = 0 + x = x. (b) Identity element 1 w.r.t.. x 1 =
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms
Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley
More informationNumber System conversions
Number System conversions Number Systems The system used to count discrete units is called number system. There are four systems of arithmetic which are often used in digital electronics. Decimal Number
More informationCombinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
More informationMinimization techniques
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationBoolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example
EES5 Section 5 Simplification and State Minimization Fall 2 -cube X oolean cubes Visual technique for indentifying when the uniting theorem can be applied n input variables = n-dimensional "cube" Y 2-cube
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationCOMBINATIONAL LOGIC FUNCTIONS
COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present
More informationLecture 4: More Boolean Algebra
Lecture 4: More Boolean Algebra Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Prof. Russell Tessier of University of Massachusetts Aby George of Wayne State University ENGIN2
More informationIntroduction to Karnaugh Maps
Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for
More informationCHAPTER 12 Boolean Algebra
318 Chapter 12 Boolean Algebra CHAPTER 12 Boolean Algebra SECTION 12.1 Boolean Functions 2. a) Since x 1 = x, the only solution is x = 0. b) Since 0 + 0 = 0 and 1 + 1 = 1, the only solution is x = 0. c)
More informationLecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions
EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The
More informationChapter 2: Princess Sumaya Univ. Computer Engineering Dept.
hapter 2: Princess Sumaya Univ. omputer Engineering Dept. Basic Definitions Binary Operators AND z = x y = x y z=1 if x=1 AND y=1 OR z = x + y z=1 if x=1 OR y=1 NOT z = x = x z=1 if x=0 Boolean Algebra
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
More informationCs302 Quiz for MID TERM Exam Solved
Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationCSE370 HW3 Solutions (Winter 2010)
CSE370 HW3 Solutions (Winter 2010) 1. CL2e, 4.9 We are asked to implement the function f(a,,c,,e) = A + C + + + CE using the smallest possible multiplexer. We can t use any extra gates or the complement
More informationEEE130 Digital Electronics I Lecture #4
EEE130 Digital Electronics I Lecture #4 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi Topics to be discussed 4-1 Boolean Operations and Expressions 4-2 Laws and Rules of Boolean
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2017 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables,,... represent classes
More informationEC-121 Digital Logic Design
EC-121 Digital Logic Design Lecture 2 [Updated on 02-04-18] Boolean Algebra and Logic Gates Dr Hashim Ali Spring 2018 Department of Computer Science and Engineering HITEC University Taxila!1 Overview What
More informationLecture 2. Notes. Notes. Notes. Boolean algebra and optimizing logic functions. BTF Electronics Fundamentals August 2014
Lecture 2 Electronics ndreas Electronics oolean algebra and optimizing logic functions TF322 - Electronics Fundamentals ugust 24 Exercise ndreas ern University of pplied Sciences Rev. 946f32 2. of oolean
More informationECE 2300 Digital Logic & Computer Organization
ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed
More informationChapter 2 : Boolean Algebra and Logic Gates
Chapter 2 : Boolean Algebra and Logic Gates By Electrical Engineering Department College of Engineering King Saud University 1431-1432 2.1. Basic Definitions 2.2. Basic Theorems and Properties of Boolean
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28
More informationReview for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
More informationOutcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More information