Textbook: Digital Design, 3 rd. Edition M. Morris Mano

Transcription

1 : 25/5/ P-/70 Tetbook: Digital Design, 3 rd. Edition M. Morris Mano Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU kevinsu@yuntech.edu.tw

2 Chapter 3 25/5/ P-2/70 Chapter 3 Gate-Level Minimization

3 Outline of Chapter 3 25/5/ P-3/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

4 3. The Map Method 25/5/ P-4/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

5 3. The Map Method 25/5/ P-5/70 Map Simplification Methods of the oolean Function Karnaugh Map (K-Map):. is a pictorial form of the truth table 2. epress any oolean function as a sum of minterms 3. presents all possible oolean function in standard form 4. Simplify a oolean function in two standard form: sum of products or product of sums 5. the simplest K-map will be implemented the minimum number of gates

6 3. The Map Method 25/5/ P-6/70 Two-Variable K-MapK Karnaugh Map (K-Map) presents the four minterms of a two-variable function as follows y 0 y= m 0 m 0 y y m 2 m 3 = y y

7 3. The Map Method 25/5/ P-7/70 Presentation of Functions in a K-MapK Eample: F=y Eample: F = + y = y + y + y = m + m 2 + m 3 y 0 y= y 0 y= 0 0 = =

8 3. The Map Method 25/5/ P-8/70 Three-Variable K-MapK Karnaugh Map (K-Map) presents the eight minterms of a three-variable function as follows =0 yz 0 y=0 m 0 m y= 0 0 m 3 m 2 Gray-Code (Only one variable changes between two adjacent position) = m 4 m 5 m 7 m 6 z=0 z= z=0

9 3. The Map Method 25/5/ P-9/70 Three-Variable K-Map K with Minterms yz y= 0 0 m 0 m m 3 m 2 0 yz yz yz yz m 4 m 5 m 7 m 6 = yz yz yz yz z=

10 3. The Map Method 25/5/ P-0/70 Three-Variable K-Map K with Minterms Eample for a 3-variable function with its K-map: F(,y,z) = m 2 + m 3 + m 4 + m 5 = S(2,3,4,5) = y + y yz 0 y=0 y= 0 0 m 2 +m 3 = m 4 +m 5 z=

11 3. The Map Method 25/5/ P-/70 Simplify a Three-Variable oolean Function Using K-MapK F(,y,z) = S(3,4,6,7) = yz + z yz y= m 3 +m 7 = z= m 4 +m 6

12 3. The Map Method 25/5/ P-2/70 Simplify a Three-Variable oolean Function Using K-MapK F(,y,z) = S(0,2,4,6) = z yz 0 y= 0 0 = z= (m 0 +m 2 ) + (m 4 +m 6 )

13 3. The Map Method 25/5/ P-3/70 K-Map Simplify for a Three-Variable Function minterm represents a term of 3 literals 2 adjacent squares represents a term of 2 literals 4 adjacent squares represents a term of literal 8 adjacent squares represents the function =

14 3. The Map Method 25/5/ P-4/70 Simplify a Three-Variable oolean Function Using K-MapK F(,y,z) = S(0,2,4,5,6) = z + y yz 0 y= 0 0 = m 4 +m 5 z= m 0 +m 2 +m 4 +m 6

15 3. The Map Method 25/5/ P-5/70 Simplify oolean Function Using K-MapK F(A,,C) = A C + A + A C + C = S (,2,3,5,7) = C + A C = A 0 0 A= 0 C= A C

16 3.2 Four-Variable Map 25/5/ P-6/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

17 3.2 Four-Variable Map 25/5/ P-7/70 Four-Variable K-MapK Karnaugh Map (K-Map) presents the 6 minterms of a four-variable function as follows yz w m 0 m y= 0 0 m 3 m 2 Gray-Code w= 0 0 m 4 m 5 m 2 m 3 m 8 m 9 m 7 m 6 m 5 m 4 m m 0 = z= Gray-Code

18 3.2 Four-Variable Map 25/5/ P-8/70 Four-Variable K-Map K with Minterms yz w y= 0 0 yz w 0 0 m 0 m m 3 m 2 wyz w= 0 0 m 4 m 5 m 2 m 3 m 8 m 9 m 7 m 6 m 5 m 4 m m 0 = 0 0 wyz z=

19 3.2 Four-Variable Map 25/5/ P-9/70 K-Map Simplify for a Four-Variable Function minterm represents a term of 4 literals 2 adjacent squares represents a term of 3 literals 4 adjacent squares represents a term of 2 literals 8 adjacent squares represents a term of literal 6 adjacent squares represents the function =

20 3.2 Four-Variable Map 25/5/ P-20/70 Simplify a Four-Variable oolean Function Using K-MapK F(w,,y,z) = S(0,,2,4,5,6,8,9,2,3,4) = y + w z + z z w yz w y= 0 0 w= 0 0 = y' z= z

21 3.2 Four-Variable Map 25/5/ P-2/70 Simplify a Four-Variable oolean Function Using K-MapK F = A C + CD + A CD + A C = D + C + A CD CD C= A 0 0 C A= 0 0 D D= A CD =

22 3.2 Four-Variable Map 25/5/ P-22/70 Prime Implicants and Essential Prime Implicans. Prime Implicant : A product term containing the maimum possible number of adjacent squares in the K-map 2. Essential Prime Implicant : A prime implicant contains a minterm that is covered by only one prime implicant

23 3.2 Four-Variable Map 25/5/ P-23/70 Function Simplification Using Prime Implicant Essential Prime Implicants: D and D CD C A 0 0 Prime Implicants: CD, C, AD, and A CD C A 0 0 A 0 0 A 0 0 D D

24 3.2 Four-Variable Map 25/5/ P-24/70 Simplify oolean Function Using K-MapK F = S(0,2,3,5,7,8,9,0,,3,5) = D+ D +CD+AD = D+ D +CD+A = D+ D + C+AD = D+ D + C+A Essential Prime Implicants

25 3.3 Five-Variable Map 25/5/ P-25/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

26 3.3 Five-Variable Map 25/5/ P-26/70 Five-Variable K-Map: K F(A,,C,D,E) A=0 A= DE C D 0 0 DE C D 0 0 m 0 m m 3 m 2 m 6 m 7 m 9 m m 4 m 5 m 2 m 3 m 8 m 9 m 7 m 6 m 5 m 4 m m 0 C 0 0 m 20 m 2 m 28 m 29 m 24 m 25 m 23 m 22 m 3 m 30 m 27 m 26 C E E

27 3.3 Five-Variable Map 25/5/ P-27/70 The Relationship between the Number of Adjacent Squares and the Number of Literal in the Term Number of Adjacent Square Number of Literals in a Term in an n-variable Map K 2 k n=2 n=3 n=4 n=

28 3.3 Five-Variable Map 25/5/ P-28/70 Simplify the 5-variable 5 Function Using K-MapK F = S(0,2,4,6,9,3,2,23,25,29,3) = A E +D E+ACE A=0 A= DE C D 0 0 DE C D ACE C 0 0 C E D E E

29 3.4 Product of Sums Simplification 25/5/ P-29/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

30 3.4 Product of Sums Simplification 25/5/ P-30/70 SOP vs. POS. Review DeMorgen s Theorem: A Function can be epress as SOP or POS 2. Eample: F(,y,z) = S(,3,6,7)= P(0,2,4,5) y z F P 0 0 S P 0 S P 0 0 P 0 S S

31 3.4 Product of Sums Simplification 25/5/ P-3/70 Simplify Function in SOP and POS F(A,,C,D) = S(0,,2,5,8,9,0) = D + C + A C D F=(F ) =(A+CD+D ) = (A + )(C +D )( +D) CD A C A D

32 3.4 Product of Sums Simplification 25/5/ P-32/70 Gate Implementation in SOP and POS F(A,,C,D) = D + C + A C D = (A + )(C +D )( +D) D C A D F A C D D F

33 3.5 Don t-care Conditions 25/5/ P-33/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

34 3.5 Don t-care Conditions 25/5/ P-34/70 Don t-care Terms (): A don t-care term is a combination of variables whose logical value is not specified. Eg. CD has 6 don t-care terms. Decimal CD

35 3.5 Don t t Care Conditions 25/5/ P-35/70 Don t-care Terms (): A don t-care term can be assigned or 0 for simplification functions. F(w,,y,z) = S(,3,7,,5)= yz + w = yz + w z yz w Don t-care terms: d = S(0,2,5) y yz 0 0 w y 0 0 w w z z

36 3.6 NAND and NOR Implementation 25/5/ P-36/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

37 3.6 NAND and NOR Implementation 25/5/ P-37/70 NAND and NOR Gates. NAND and NOR gates are easier to fabricate with electronic components. 2. NAND and NOR gates are the basic gates in all IC digital family. 3. The Function implemented in NAND and NOR gates is important.

38 3.6 NAND and NOR Implementation 25/5/ P-38/70 NAND Gates. NAND gate is a universal gate 2. Any digital system can be implemented with NAND gates 3. Logical Operation using NAND Gates Inverter AND y y OR y ( y ) = +y

39 3.6 NAND and NOR Implementation 25/5/ P-39/70 Two Implementations for NAND Gates DeMorgans Theorem: (yz) = +y +z y z (yz) y z +y+z

40 3.6 NAND and NOR Implementation 25/5/ P-40/70 A C D F Two-Level Implementation F= A + CD = [(A) (CD) ] A C D A C D F F

41 3.6 NAND and NOR Implementation 25/5/ P-4/70 Eample: Two-Level Implementation with NAND Gates F(,y,z) = S(,2,3,4,5,7) = y + y + z yz 0 y= 0 0 = z=

42 3.6 NAND and NOR Implementation 25/5/ P-42/70 Eample: Two-Level Implementation with NAND Gates F(,y,z) = y + y + z y y F y y F z z

43 3.6 NAND and NOR Implementation 25/5/ P-43/70 The Procedure for Implementation Function with 2-level 2 NAND Gates. Simplify the function and epress it in sum of products. 2. Draw a NAND gate for each product term of the epression that has least two literals.the inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates. 3. Draw a single gate using the AND-invert or invert-or graphic symbol in the second level, with inputs coming from outputs of first level gates. 4. A term with a single literal requires an inverter in the first level. However, if the single literal is complemented, it can be connected directly to an input of the second level NAND gates.

44 3.6 NAND and NOR Implementation 25/5/ P-44/70 C D A C Multilevel NAND Circuits F(A,,C,D) = A(CD+) + C F C D A C F

45 3.6 NAND and NOR Implementation 25/5/ P-45/70 Multilevel NAND Circuits F(A,,C,D) = (A + A )( C+D ) A A C D F A A C D F

46 3.6 NAND and NOR Implementation 25/5/ P-46/70 The Procedure for Converting a Function into an All-NAND Gate Representation. Convert all AND gates to NAND gates with AND-invert graphic symbols. 2. Convert all OR gates to NAND gates with invert-or graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an invert (one-input NAND gate) or complement the input literal.

47 3.6 NAND and NOR Implementation 25/5/ P-47/70 NOR Implementation. NOR gate is a universal gate 2. Any digital system can be implemented with NOR gates Inverter OR y +y AND y ( +y ) = y

48 3.6 NAND and NOR Implementation 25/5/ P-48/70 Two Implementations for NOR Gates DeMorgans Theorem: (+y+z) = y z y z (+y+z) y z yz =(+y+z)

49 3.6 NAND and NOR Implementation 25/5/ P-49/70 Eample: Two-Level Implementation with NOR Gates A C D E F = (A+)(C+D)E F A C D F E

50 3.6 NAND and NOR Implementation 25/5/ P-50/70 A A C D A A C D Multilevel NOR Circuits F(A,,C,D) = (A + A )( C+D ) F F

51 3.7 Other Two-Level Implementations 25/5/ P-5/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

52 3.7 Other Two-Level Implementations 25/5/ P-52/70 Wired Logic A C D A C D F = (A) (CD) = (A+CD) Wired-AND = (A+) + (C+D) = [(A+)(C+D)] Wired-OR F=(A+CD) : Wired-AND F=[(A+)(C+D)] : Wired-OR

53 3.7 Other Two-Level Implementations 25/5/ P-53/70 Non-degenerate Forms Two-level Function Implementation with. AND 2. OR 3. NAND 4. NOR Therefore, 6 possible combinations. The 8 non-degenerate combinations are. AND-OR (3.4) 5. OR-AND (3.4) 2. NAND-NAND (3.6) 6. NOR-NOR (3.6) 3. NOR-OR 7. NAND-AND 4. OR-NAND 8. AND-NOR

54 3.7 Other Two-Level Implementations 25/5/ P-54/70 AND-OR OR-INVERT Implementation F = (A+CD+E) A C D F A C D F A C D F E AND-NOR (AND-OR-INVERT) E AND-NOR E NAND-AND

55 3.7 Other Two-Level Implementations 25/5/ P-55/70 OR-AND AND-INVERT Implementation F = [(A+)(C+D)E] A C D F A C D F A C D F E OR-NAND (OR-AND-INVERT) E OR-NAND E NOR-OR

56 3.7 Other Two-Level Implementations 25/5/ P-56/70 Implementation with Other Two-Level Forms Equivalent Implements Simplify To Get Non-degenerate the F and Output Form Function in of (a) (b) AND-NOR NAND-AND AND-OR-INVERT Sum of products F by combining 0's in the K-map OR-NAND NOR-OR OR-AND-INVERT Product of sum by F combining 's in the K-map and then complementing Table 3-3

57 3.7 Other Two-Level Implementations 25/5/ P-57/70 Eample Implementation F with the 4 two-level forms in Table 3-3 = yz y= F = y z + yz F = y + y + z z= y y F y y F z AND-NOR z F= ( y+y +z) NAND-AND

58 y z y z 3.7 Other Two-Level Implementations 25/5/ P-58/70 Eample Implementation F with the 4 two-level forms in Table 3-3 = yz y= 0 0 z= F = y z + yz F = y + y + z y z y z F F OR-NAND NOR-OR F= [(+y+z)( +y +z)]

59 3.8 Eclusive-OR Function 25/5/ P-59/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)

60 3.8 Eclusive-OR Function 25/5/ P-60/70 Eclusive-OR (XOR) Eclusive-OR + y y + y Eclusive-NOR ( + y) y + y Commutative + y = y + Associative ( + y) + z = + (y + z) = + y + z

61 3.8 Eclusive-OR Function 25/5/ P-6/70 Eclusive-OR Implementations + y : AND-OR-NOT y + y : NAND Gates y

62 3.8 Eclusive-OR Function 25/5/ P-62/70 Primitive Eclusive-OR Operations. + 0 = 2. + = 3. + = = 5. + y = + y = ( + y)

63 3.8 Eclusive-OR Function 25/5/ P-63/70 Odd Function Function with odd number of input variables is equal to yz A + + C = (A + A )C + (A + A )C = A C + A C + AC + A C = Σ (,2,4,7) y= 0 0 yz y= = = z= z= Odd Function : F = A + + C Even Function : F = (A + + C)

64 3.8 Eclusive-OR Function 25/5/ P-64/70 Logic Implementation A C F: 3 Input Odd Function A C F: 3 Input Even Function

65 3.8 Eclusive-OR Function 25/5/ P-65/70 yz w Four-Variable Eclusive-OR Function A + + C + D = Σ (,2,4,7,8,,3,4) y= 0 0 yz w y= 0 0 w= 0 0 = w= 0 0 = z= Odd Function z= Even Function

66 3.8 Eclusive-OR Function 25/5/ P-66/70 Parity Generation and Checking. XOR is used in error-detection and error-correction. 2. Parity bits are etra bits with the data to make its number of s either odd or even. 3. The odd/even parity data is transmitted for error detection. 4. The circuit that generates the parity bit in the transmitter is called a parity generator. 5. The circuit that checks the parity in the receiver is called a parity checker.

67 3.8 Eclusive-OR Function 25/5/ P-67/70 Parity Data Transmission System Source Data n bits Source Data Parity Generator n bits n+ bits Even/Odd Data Parity bits: bit Data Transmission Parity Checker n+ bits Even/Odd Data

68 3.8 Eclusive-OR Function 25/5/ P-68/70 Even-Parity Parity-Generator Truth Table Three-it Data Parity it y z P

69 3.8 Eclusive-OR Function 25/5/ P-69/70 Logic Implementation of Parity Generator and Checker y z P = + y + z C = + y + z + P Data Transmission y P z P C

70 3.9 Hardware Description Language (HDL) 25/5/ P-70/70 3. The Map Method 3.2 Four-Variable Map 3.3 Five-Variable Map 3.4 Product of Sums Simplification 3.5 Don t-care Conditions 3.6 NAND and NOR Implementation 3.7 Other Two-Level Implementations 3.8 Eclusive-OR Function 3.9 Hardware Description Language (HDL)