CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

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1 MS 33 Lecture 8 Midterm Exam returned Assign Homework 3 ircuits for Addition Digital Logic omponents Programmable Logic Arrays UMB, MS33, Richard hang <chang@umbc.edu>

2 MS 33, omputer Organization & Assembly Language Programming, section Fall 24 Homework 3 Due: November, 24. (3 points) Draw schematics for the following functions using AND, OR and NOT gates. (Do not simplify the formulas.) (a) XY + XY Z + XY Z (b) (XY + WZ)(WX + Y Z) (c) (X + Y )(X + Y ) 2. (3 points) Using the postulates and theorems of Boolean algebra in Table A- (p. 45), simplify the following formulas. Show all of your work. (a) WXY Z(WXY Z + WXY Z + WXY Z + WXY Z) (b) AB + ABD + ABDE + ABE + DE (c) MNO + QPN + PRM + QOMP + MR 3. (4 points) For each MOS circuit below, (a) Provide a truth table for the circuit s function. (b) For diagram (a), write down the Sum-of-Products (SOP) Boolean formula for the truth table. For diagram (b), wrtie down the Product-of-Sums (POS) Boolean formula. (c) Simplify the SOP or POS formula using the postulates and theorems of Boolean Algebra (p. 45). Show all work. (d) Draw the logic diagram of the simplified formula using AND, OR, NAND, NOR and NOT gates. +5v A +5v A B z B z D D GND GND (a) (b)

3 Last Time Postulates & Theorems of Boolean Algebra Periodic Table & Semiconductors P-N junction Field-Effect Transistors MOS Logic Gates UMB, MS33, Richard hang

4 Half Adder Inputs: A and B Outputs: S = lower bit of A + B, c out = carry bit A B S c out Using Sum-of-Products: S = AB + AB, c out = AB. Alternatively, we could use XOR: S = A B.

5 Adder Inputs: A, B and c in Outputs: S = lower bit of A + B, c out = carry bit A B c in S c out S = AB + AB + AB + AB = A B. c out = MAJ3 = AB + B + A. 2

6 3-6 Ripple arry Adder hapter 3: Arithmetic Two binary numbers A and B are added from right to left, creating a sum and a carry at the outputs of each full for each bit position. b 3 a 3 c 3 b 2 a 2 c 2 b a c b a c c 4 s 3 s 2 s s 999 M. Murdocca and V. Heuring

7 3-7 onstructing Larger Adders hapter 3: Arithmetic A 6-bit can be made up of a cascade of four 4-bit ripplecarry s. a 5 a 4 a 3 a 2 b 5 b 4 b 3 b 2 b 3 a 3 b 2 a 2 b a b a c 6 4-Bit Adder #3 c 2 c 4 c... 4-Bit Adder # s 5 s 4 s 3 s 2 s 3 s 2 s s 999 M. Murdocca and V. Heuring

8 3-8 Subtractor hapter 3: Arithmetic Truth table and schematic symbol for a ripple-borrow subtractor: a i b i bor i diff i bor i+ b i a i bor i+ subtractor diff i (a i b i ) bori 999 M. Murdocca and V. Heuring

9 3-9 Ripple-Borrow Subtractor hapter 3: Arithmetic A ripple-borrow subtractor can be composed of a cascade of full subtractors. Two binary numbers A and B are subtracted from right to left, creating a difference and a borrow at the outputs of each full subtractor for each bit position. b 3 a 3 b 2 a 2 b a b a bor subtractor subtractor subtractor subtractor bor 4 diff 3 diff 2 diff diff 999 M. Murdocca and V. Heuring

10 3- ombined Adder/Subtractor hapter 3: Arithmetic A single ripple-carry can perform both addition and subtraction, by forming the two s complement negative for B when subtracting. (Note that + is added at c for two s complement.) b 3 b 2 b b ADD / SUBTRAT a 3 a 2 a a c c 4 s 3 s 2 s s 999 M. Murdocca and V. Heuring

11 3-2 arry-lookahead Addition hapter 3: Arithmetic arries are represented in terms of G i (generate) and P i (propagate) expressions. G i = a i b i and P i = a i + b i c = c = G c 2 = G + P G c 3 = G 2 + P 2 G + P 2 P G c 4 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G 999 M. Murdocca and V. Heuring

12 3-22 arry Lookahead Adder hapter 3: Arithmetic b 3 a 3 b 2 a 2 b a b a G 3 P 3 G 2 P 2 G P G Maximum gate delay for the carry generation is only 3. The full s introduce two more gate delays. Worst case path is 5 gate delays. c 4 c 3 c 2 c c s 3 s 2 s s 999 M. Murdocca and V. Heuring

13 A-26 Appendix A: Digital Logic Digital omponents High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates. Levels of integration (numbers of gates) in an integrated circuit (I) can roughly be considered as: Small scale integration (SSI): - gates. Medium scale integration (MSI): to gates. Large scale integration (LSI): -, logic gates. Very large scale integration (VLSI):,-upward logic gates. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. 999 M. Murdocca and V. Heuring

14 Data Inputs A-27 Appendix A: Digital Logic Multiplexer D D D 2 D 3 F A B F D D D 2 D 3 A B ontrol Inputs F = A BD + A B D + A B D 2 + A B D M. Murdocca and V. Heuring

15 A-28 Appendix A: Digital Logic AND-OR Implementation of MUX D D D 2 F D 3 A B 999 M. Murdocca and V. Heuring

16 A-29 Appendix A: Digital Logic MUX Implementation of Majority Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs. A B M F A B 999 M. Murdocca and V. Heuring

17 A-3 Appendix A: Digital Logic 4-to- MUX Implements 3-Var Function Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX data input is selected from {,,, } to achieve the desired behavior of the minterm pair. A B F A B F 999 M. Murdocca and V. Heuring

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