CMPT-150-e1: Introduction to Computer Design Final Exam

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1 CMPT-150-e1: Introduction to Computer Design Final Exam April 13, 2007 First name(s): Surname: Student ID: Instructions: No aids are allowed in this exam. Make sure to fill in your details. Write your answers neatly on these sheets. Use the exam booklet provided to you for your drafts. There are 10 questions in 14 pages in this exam, please attempt all. The last 4 pages contain relevant assembler directives and instructions. Next to every question appears a suggested time to spend on the question. Total marks: 110. Time: 3 hours. Question 1 [5 minutes, 5 marks] A state diagram for a sequential circuit has M states. We wish to assign each of the states a unique name which is an n-bit binary word. What is the smallest value of n that we can use? Explain. n bits can represent 2 n different binary words. Therefore, n is an integer such that 2 n-1 < M 2 n, thus, n = log 2 M. Question 2 What is register PC used for in the CPU12? [2 minutes, 5 marks] Register PC contains the address of the next instruction to be executed.

2 Question 3 [3 minutes, 5 marks] Describe the difference between the Mealy model and the Moore model for sequential circuits. In the Mealy model the output signals are Boolean functions of the input signals and the current state, while in the Moore model the output signals depends only on the current state. Question 4 Describe the steps of the fetch-execute cycle of a CPU. [5 minutes, 5 marks] 1. Fetch the next instruction to be executed from memory. 2. Decode the instruction. 3. Execute the instruction and (possibly) store the result. 4. Go back to step 1. Question 5 [25 minutes, 15 marks] Design a combinatorial circuit that converts a 3-bit signed number from sign-magnitude representation to 2 s complement representation. Denote the input by XYZ (X is the most significant bit) and the output by ABC (A is the most significant bit). a. Complete the truth table for the circuit. X Y Z A B C

3 b. Write A and B as sum of minterms, and C as a product of maxterms. Use both short and explicit representations. A = ( 5,6,7) = m XYZ + XYZ + XYZ B = ( 2,3,5,6) = XYZ + XYZ + XYZ + XYZ m C = M ( 0,2,4,6) = ( X + Y + Z)( X + Y + Z)( X + Y + Z)( X + Y + Z) c. Obtain a minimized SOP representation for each output signal using K-Maps. Specify the essential and prime implicants in each K-Map. A B C YZ X X YZ YZ X Prime Implicants: Prime Implicants: Prime Implicants: XZ, XY X YZ, YZ, XY Z Essential Implicants: Essential Implicants: Essential Implicants: XZ, XY X YZ, YZ, XY Z A = XZ + XY B = XYZ + YZ + XY C = Z Question 6 [10 minutes, 10 marks] Instead of using CPU12 s stack and stack pointer, it is possible to use a user-defined stack, which is pointed by register IX or IY. In the following code such a stack is defined using IX as a pointer for the stack. Complete the missing instructions for pushing the content of Accumulator A into the stack and then pulling the value at the top of the stack into Accumulator B.

4 MY_STACK EQU $2000 ORG $0800 ENTRY: LDX #MY_STACK ; IX <-- $2000 LDAA #$90 ; A <-- $90 STAA $1,-X ; IX <-- IX-1, Mem[IX] <-- A LDAB $1,X+ ; B <-- Mem[IX], IX <-- IX+1 Question 7 [15 minutes, 10 marks] The 8 outputs of a 3-to-8 decoder are connected to the information inputs of an 8-to-1 MUX as shown. a b c D 0 I 0 S 2 S 1 S 0 D 1 I 1 z y x A 0 A 1 A 2 3-to-8 Decoder D 2 I 2 D 3 I 3 D 4 I 4 D 5 I 5 8-to-1 MUX f D 6 I 6 D 7 I 7 Denote the inputs to the decoder by x,y,z and the select inputs of the MUX by a,b,c. Express the single output f of the MUX in terms of x,y,z,a,b,c in a SOP representation. Solution: f = xyzab c + xyzab c + xyzabc + xyzab c + xyzabc + xyzab c + xyzabc + xyzabc Question 8 [40 minutes, 20 marks] You are to design a controller (sequential circuit) for an elevator in a four-floor building with no basement (that is, the floors are numbered 0,1,2, and 3). To simplify things, assume the elevator can only be summoned to one floor. The desired floor is indicated by a 2-bit unsigned binary number A 1 A 0 (for example, A 1=1 and A0=0 means the elevator is summoned to floor 2). The controller has two outputs: M a move signal which is 1 if the elevator is moving and 0 otherwise. For example, if the elevator is currently at floor 2 and A 1 A 0 =10, then M=0. D a direction signal which is 1 if the elevator is moving up and 0 if the elevator is moving down. If the elevator is not moving this signal is ignored.

5 Assume that the elevator is initially at floor 0 and that it takes the elevator one clock cycle to move one floor. a. Write the state diagram of the controller. Use the Mealy model. What represents each state? The states represent the current location (floor) of the elevator. 01,10,11/1,1 10,11/1,1 11/1,1 00/1,0 00,01/1, ,01,10/1,0 3 00/0,X 01/0,X 10/0,X 11/0,X b. Assign names to the states and complete the state table of the controller. F 1 and F 0 represent the current state. (The last two columns are there to help you answer the next section. You may leave them empty.) We assign names according to the floor number. A 1 0 F F 1 F 0 T1 T0 A M D X X X X

6 c. Assuming the controller is to be implemented using T flip-flops and basic gates (NOT and multiple inputs AND and OR gates), obtain minimized equations for each output signal and each T signal of a T flip-flop. Justify the equations you obtained. Recall the characteristic table of a T flip-flop: T Q + 0 Q 1 Q F 1 F1F 0 A 1 A 0 A 1 A X X X X T + 0 = M = A1 F1 + A1 F1 + A0 A0 D = A1 F1 + A1 A0 + F1 - A 0F1 can replace F 0F1 - A 1 can replace A 1 A0 F 1 F 0 A 1 A T + 1 = A1 F1 A1 F1

7 Question 9 Consider the following assembler code. [40 minutes, 20 marks] Address Machine Addressing Effective Code (Hex) Mode Address(es) 1 ORG $ FF VALUES: FCB $4,$2,$0,$1,$FF 3 ORG $ CF ENTRY: LDS #ENTRY Immediate LDAA VALUES Direct CE LDX #VALUES Immediate E6 E4 LDAB A,X Register 0004 Offset Indexed 8 080A LOOP: ABA Implied 9 080C 2C FC BGE LOOP Relative E A6 20 LDAA $1,+X Pre-auto 0001 Increment 0002 Indexed F8 BNE LOOP Relative C7 CLRB Implied E6 E7 LDAB [D,X] Indirect Register Indexed F SWI A6 NOP 0001 a. Determine the addressing mode of every assembly instruction (do not fill shaded cells). b. Fill in the address in memory and machine code for the constants in line 2 and for every assembly instruction (do not fill shaded cells). c. Determine the effective address of every assembly instruction (do not fill shaded cells). If the instruction is executed more than once, and different effective addresses are used, write them all. d. How many times is line 8 executed? 8 e. What is the content (in binary) of register D when the program terminates?

8 Question 10 Consider the following partial assembler code: ORG $0000 VAL1: FCB $10 VAL2: FCB $20 [20 minutes, 15 marks] ORG $0800 ENTRY: LDS #ENTRY LDAA #$15 LDX #VAL1 PSHX PSHA JSR MY_MAX ; now VAL1 contains $15 LEAS $3,SP ; SP <-- SP+3 LDX #VAL2 PSHX PSHA JSR MY_MAX ; now VAL2 contains $20 LEAS $3,SP ; SP <-- SP+3 ; halt instructions SWI NOP ORG $8000 MY_MAX: PSHA LDAA [$4,SP] SUBA $3,SP BGE MY_MAX_END LDAA $3,SP STAA [$4,SP] MY_MAX_END: PULA RTS a. Complete the missing instructions in the code. b. How many parameters are passed to subroutine MY_MAX? What parameter-passing technique is used for each parameter? MY_MAX receives two parameters. The first parameter is passed by reference (its address is stored on the stack), while the second parameter (appears higher on the stack) is passed by value. c. Describe the functionality of subroutine MY_MAX. The first value (the one passed by address) is replaced by the second value, if the second value is greater than the first value.

Computer Science Final Examination Friday December 14 th 2001

Computer Science Final Examination Friday December 14 th 2001 Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,