Karnaugh Maps (K-Maps)

Transcription

1 Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC BC = BC + BC = B(C + C ) Chapter 2 <4>

2 K-Map Circle s in adjacent squares In Boolean expression, include only literals whose true and complement form are not in the circle B C C B = B C not included because both C and C included in circle Chapter 2 <4>

3 3-Input K-Map B C BC BC BC BC BC BC BC BC Truth Table B C K-Map B C Chapter 2 <42>

4 K-Map Definitions Complement: variable with a bar over it, B, C Literal: variable or its complement,, B, B, C, C Implicant: product of literals BC, C, BC Prime implicant: implicant corresponding to the largest circle in a K-map Chapter 2 <43>

5 K-Map Rules Every must be circled at least once Each circle must span a power of 2 (i.e., 2, 4) squares in each direction Each circle must be as large as possible circle may wrap around the edges don't care () is circled only if it helps minimize the equation Chapter 2 <44>

6 4-Input K-Map B C D B CD Chapter 2 <45>

7 4-Input K-Map B C D B CD Chapter 2 <46>

8 4-Input K-Map B C D CD B = C + BD + BC + BD Chapter 2 <47>

9 K-Maps with Don t Cares B C D B CD Chapter 2 <48>

10 K-Maps with Don t Cares B C D B CD Chapter 2 <49>

11 K-Maps with Don t Cares B C D B CD = + BD + C Chapter 2 <5>

12 4-Input K-Map: POS & SOP Form B C D B CD Chapter 2 <5>

13 4-Input K-Map: POS Form B C D CD B = C + BD + BC + BD Chapter 2 <52>

14 4-Input K-Map: SOP Form B C D B CD Chapter 2 <53>

15 Canonical POS Expansion dd literal/complement terms to reverse simplification ( expand literal) Example = C = C + = C + (C + ) = [ C + + BB](C + ) = C + + B C + + B C + Chapter 2 <54>

16 Combinational Building Blocks Multiplexers Decoders Chapter 2 <55>

17 Multiplexer (Mux) Selects between one of N inputs to connect to output log 2 N-bit required to select input control input S Example: 2: Mux (2 inputs to output) N = 2 log 2 2 = control bit required S D D D D S S D D Chapter 2 <56>

18 Multiplexer Implementations Logic gates Sum-of-products form D D S Tristates For an N-input mux, use N tristates Turn on exactly one to select the appropriate input S = D S + D S D D D S D Chapter 2 <57> 2-<57>

19 Logic using Multiplexers Using the mux as a lookup table Zero outputs tied to GND One output tied to VDD B = B B Chapter 2 <58>

20 Logic using Multiplexers Reducing the size of the mux = B B B B Chapter 2 <59>

21 Decoders N inputs, 2 N outputs One-hot outputs: only one output HIGH at once Example 2:4 Decoder (2 inputs to 4 outputs) i decimal value selects the corresponding output 2:4 Decoder Chapter 2 <6>

22 Decoder Implementation 3 2 Chapter 2 <6>

23 Logic Using Decoders OR minterms B 2:4 Decoder Minterm B B B B = B + B = B NOR function Chapter 2 <62>

24 Timing Delay between input change and output changing delay Time How to build fast circuits? Chapter 2 <63>

25 Propagation & Contamination Delay Propagation delay: t pd = max delay from input to final output Contamination delay: t cd = min delay from input to initial output change t pd Note: Timing diagram shows a signal with a high and low and transition time as an. Cross hatch indicates unknown/changing values t cd Time Chapter 2 <64>

26 Propagation & Contamination Delay Delay is caused by Capacitance and resistance in a circuit Speed of light limitation Reasons why t pd and t cd may be different: Different rising and falling delays Multiple inputs and outputs, some of which are faster than others Circuits slow down when hot and speed up when cold Chapter 2 <65>

27 Critical (Long) & Short Paths Critical Path B C D n Short Path n2 Critical (Long) Path: t pd = 2t pd_nd + t pd_or Short Path: t cd = t cd_nd Chapter 2 <66>

28 Glitches When a single input change causes an output to change multiple times Chapter 2 <67>

29 Glitch Example What happens when =, C =, B falls? B C C B = B + BC Chapter 2 <68>

30 Glitch Example (cont.) = B = C = Critical Path n n2 = Short Path B n2 n Note: n is slower than n2 because of the extra inverter for B to go through glitch Time Chapter 2 <69>

31 Fixing the Glitch C B Consensus term C = B + BC + C = B = = C = Chapter 2 <7>

32 Why Understand Glitches? Glitches shouldn t cause problems because of synchronous design conventions (see Chapter 3) It s important to recognize a glitch: in simulations or on oscilloscope Can t get rid of all glitches simultaneous transitions on multiple inputs can also cause glitches Chapter 2 <7>