211: Computer Architecture Summer 2016
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1 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic
2 - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean Algebra / K-map Rutgers University Liu Liu 2
3 - Digital Logic: Today s Topic - Review: truth table => SOP => simplification - dual / complement - Minterm / Maxterm - SOP <=> POS - Combinational Circuit - Full Adder / Overflow Rutgers University Liu Liu 3
4 DeMorgan's Law Converting AND to OR (with some help from NOT) Consider the following gate: A B A B A B A B To convert AND to OR (or vice versa), invert inputs and output. Generally, DeMorgan s Laws: 1. PQ = P + Q 2. P + Q = P Q Same as A+B! Rutgers University Liu Liu 4
5 Converting Truth Table to Boolean Expression Given a circuit, isolate the rows in which the output of the circuit should be true Rutgers University Liu Liu 5
6 Converting Truth Table to Boolean Expression Given a circuit, isolate that rows in which the output of the circuit should be true A product term that contains exactly one instance of every variable is called a minterm Rutgers University Liu Liu 6
7 Converting Truth Table to Boolean Expression Given the expressions for each row, build a larger Boolean expression for the entire table. This is a sum-of-products (SOP) form. Rutgers University Liu Liu 7
8 Converting Truth Table to Boolean Expression Finally build the circuit. Problem: SOP forms are often not minimal. Solution: Make it minimal. We ll go over two ways. Rutgers University Liu Liu 8
9 Boolean Identities Rutgers University Liu Liu 9
10 Boolean Algebra Example Rutgers University Liu Liu 10
11 Using DeMorgan s Laws to Complement 1. To big bar over AND and OR of 2 or more functions 2. Replace AND with OR, OR with AND 3. 1 with 0, 0 with 1 4. F with not(f), not(f) with F Rutgers University Liu Liu 11
12 Karnaugh Maps or K-Maps K-maps are a graphical technique to view minterms and how they relate. The map is a diagram made up of squares, with each square representing a single minterm. Minterms resulting in a 1 are marked as 1, all others are marked 0 Rutgers University Liu Liu 12
13 Simplify Example Rutgers University Liu Liu 35 13
14 Simplify Example Rutgers University Liu Liu 36 14
15 3 Variable K-Maps C Note in higher maps, several variables occupy a given axis The sequence of 1s and 0s follow a Gray Code Sequence. (WHY?) B Rutgers University Liu Liu 15
16 3 Variable K-Maps Rutgers University Liu Liu 16
17 3 Variable K-Maps Rutgers University Liu Liu 17
18 Back to our earlier example.. The K-map and the algebraic produce the same result. Rutgers University Liu Liu 43 18
19 New:NAND and NOR Functional Completeness Any gate can be implemented using either NOR or NAND gates. Why is this important? When building a chip, easier to build one with all of the same gates. How? Rutgers University Liu Liu 19
20 Duals All boolean expressions E have duals E* if(e), we cannot tell E* if(e1 <=> E2), we can tell E1* <=> E2* To form a dual 1. replace AND with OR, OR with AND 2. replace 1 with 0, 0 with 1 Rutgers University Liu Liu 20
21 Complement All boolean expressions E have complements E if(e) then E = false if(e1 <=> E2), then E1 <=> E2 Any theorem you prove, you can also prove for the complement To form a complement 1. replace AND with OR, OR with AND 2. replace 1 with 0, 0 with 1 3. replace X to X Rutgers University Liu Liu 21
22 Relationship between Complement and Duals Rutgers University Liu Liu 22
23 Get complement equation of F = AB + CD F = A + ( BC) Examples Get Dual of: A+(B+C) = (A+B)+C Rutgers University Liu Liu 23
24 Complement Using Duals Get dual and then complement each literal Rutgers University Liu Liu 24
25 Using Duals for Gate Manipulation Rutgers University Liu Liu 25
26 Converting Circuits to all-nand (NOR) Go from left to right When manipulating AND/OR gate, stick in pairs of NOT gates Isolated NOT gates can be implemented as NAND (NOR) Rutgers University Liu Liu 26
27 Example what else can we do with dual/complement? Rutgers University Liu Liu 27
28 Canonical Forms We have studied two canonical forms 1. Sum of Products (SoP) 2. Product of Sums (PoS) How to convert to SoP from PoS (multiply through) How to convert to PoS from SoP (complement twice, in between multiply through) Rutgers University Liu Liu 28
29 Formal Definition of Minterms Rutgers University Liu Liu 29
30 Minterm Example Rutgers University Liu Liu 30
31 Formal Definition of Maxterms Rutgers University Liu Liu 31
32 Maxterm Example Rutgers University Liu Liu 32
33 Converting Between Canonical Forms Rutgers University Liu Liu 33
34 K-maps and Implicants Rutgers University Liu Liu 34
35 Implicants Rutgers University Liu Liu 35
36 More Implicant Terminology Implicant: product term, which when viewed in a K-map, is a rectangle of 1s Prime implicant: an implicant not contained in another implicant Essential prime implicant: a prime implicant that is the only prime implicant to cover some minterm Rutgers University Liu Liu 36
37 Example Rutgers University Liu Liu 37
38 Example Rutgers University Liu Liu 38
39 Product of Sums Example Rutgers University Liu Liu 39
40 Don t Care Conditions Rutgers University Liu Liu 40
41 Don t Cares can Greatly Simplify Circuits Rutgers University Liu Liu 41
42 Break Rutgers University Liu Liu 42
43 Stateless circuits Combinational Circuits Outputs are functions of inputs only Rutgers University Liu Liu 43
44 Enabler Circuits Rutgers University Liu Liu 44
45 Decoder Circuits Rutgers University Liu Liu 45
46 Decoder Example Rutgers University Liu Liu 46
47 Internal 2:4 Decoder Design Rutgers University Liu Liu 47
48 2:4 Decoder from 1:2 Decoders Rutgers University Liu Liu 48
49 Hierarchical 3:8 Decoder Rutgers University Liu Liu 49
50 Encoder: Inverse of Decoder Inverse of decoder: converts m bit input to n bit output (n <= m) Rutgers University Liu Liu 50
51 Design Example Rutgers University Liu Liu 51
52 Design Example Rutgers University Liu Liu 52
53 Design Example We will do f, but you should be able to design a-e as well Rutgers University Liu Liu 53
54 Multiplexers (Muxes) Combinational circuit that selects binary information from many inputs to one output Rutgers University Liu Liu 54
55 Internal Mux Organization Rutgers University Liu Liu 55
56 Mux Truth Table Rutgers University Liu Liu 56
57 Demultiplexer (Demux) Rutgers University Liu Liu 57
58 Functions with Decoders or Muxes Rutgers University Liu Liu 58
59 A Mux Trick Can actually use a smaller mux with a trick: Look at the rows below, A & B have the same value, C iterates between 0 & 1 For the pair of rows, F either equals 0 or 1, C or not(c) Rutgers University Liu Liu 59
60 Another Mux Trick Rutgers University Liu Liu 60
61 Addition: The Half Adder Addition of 2 bits: A & B produces summand (S) and carry (C) But to do addition, we need 3 bits at a time (to account for carries) Rutgers University Liu Liu 61
62 The Full Adder Takes as input 2 digits (A&B) and previous carry (P) Rutgers University Liu Liu 62
63 5-bit Ripple Carry Adder Note how computation ripples from left to right Each adder has depth 2 (input passes through 2 gates to reach output) Full adder that computes s i cannot start its computation until previous full adder computes carry The longest depth in a k-bit ripple carry adder is 2k Rutgers University Liu Liu 63
64 Adder/Subtractor in 2 s Complement Form Recall A-B = A+(-B) Rutgers University Liu Liu 64
65 Handling Overflow Rutgers University Liu Liu 65
66 Overflow Computation in Adder/Subtractor For 2s complement, overflow if 2 most significant carries differ Rutgers University Liu Liu 66
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