Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).

Transcription

1 hapter : oolean lgebra.) Definition of oolean lgebra The oolean algebra is named after George ool who developed this algebra (854) in order to analyze logical problems. n example to such problem is: Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both). We use the formal definition of the oolean algebra as given by E. V. Huntington in 94: oolean algebra is an algebraic structure defined on a set of variables along with two binary operators and so that the six Huntington rules shown below are satisfied. efore we give these six rules, we define the terms binary operator and a closed set: binary operator is defined on a set and is a rule assigning a single member of to any pair of. closed set in relation to a binary operator: If applying the operator on any pair of members belonging to results with a member of, the set is close set in relation to that operator. Huntington rules; I) The set is closed in relation to the operators and. II) unitary member for is denoted by and satisfies: X X unitary member for is denoted by and satisfies: X b X III) The operators and are commutative, i.e., X ƒ ƒ X and X b b X IV) The operators and are distributive, i.e., X b ( ƒ Z) ( X b ) ƒ ( X b Z) and X ƒ ( b Z ) ( X ƒ ) b ( X ƒ Z) V) ny member X of has a complement X so that X X and X X VI) The set has at least two members We deal with i-level or inary oolean algebra in which the set contains only two possible values, and, i.e., {, }. We call the operator the logical OR operator and the operator, the logical ND operator. The logical OR operation has 4 possible combinations: ƒ

2 hapter : oolean lgebra 2 Note that the result is if the first operand OR the second (or both) are. This is the reason for naming this operator the OR operator. The logical ND operation has also 4 possible combinations: Note that the result is only if the first operand ND the second one are. This is the reason for naming this operator the ND operator. The complement operation is called NOT and is marked by a bar over the variable. Here we have only two possible cases: Let us verify that Huntington rules are satisfied: I) We see that any combination of OR and ND results with a member of. II) The 2 nd rule is satisfied since: and so, for any possible value of X we have X X similarly, and, so for any value of X we have X X III) We see that the operators and are commutative. IV) We can easily see that if X, then both sides of the equation X b ( Z) ( X b ) ( X b Z) are. If X, the left hand side of the equation is if or Z are, but so is the right hand side of that equation. Similarly, we can show this also for the equation X ( b Z) ( X ) b ( X Z). V) Is straight forward according the definition of the NOT operation VI) Is straight forward. We can now describe the example given above using the language of oolean algebra. is if fat and if not fat. is if triangle and if not triangle. These two notions of fat and triangle just describe some property of something, that may or may not exist. If we denote the property green by, we can define the problem as follows: Prove that if Or even: if b then α then means.

3 hapter : oolean lgebra 3.2) Venn diagrams We may use Venn diagrams to visually describe the logical relations of such equations. The rectangle stands for all possible cases (e.g., fat and triangle, green and not triangle etc.). The circle represents all cases in which, i.e., in which that something we discuss is fat. The shaded area therefore, represents all cases in which, i.e.,. Figure.-Venn diagram of a single variable In Figure2, the left hand side circle represents, while the right hand side circle represents, i.e., all cases in which, which means that the something we discuss is fat. The cases included in the expression are represented by the union of the circles representing and. The intersection of the two circles represents. The shaded area, is therefore all cases in which are and at the same time also, i.e.,. Figure.2- Venn diagram of two variables

4 hapter : oolean lgebra 4 Since if (or α ), must include, i.e., is even larger than the shaded area in figure 2. In Figure 3, we see that is therefore smaller than. This means that in case is, we must also have which is exactly what we wanted to prove. y the way, the area included in but without represents α. Figure.3- Explanation of the example So we see that Venn diagrams can be helpful when we try to visually solve, or understand, logical problems.

5 hapter : oolean lgebra 5.3) asic Identities nother way to solve or simplify logical equations, is to use some basic laws or identities. The following table, describe basic laws that are useful in manipulation of oolean equations. X X (Identity law) X X 2 X X (inverse law) X X 3 X (one law) X (zero law) 4 X X X X X X 5 ( X ) X 6 X X (ommutative law) 7 ( X ) Z X ( Z) (ssociative law) 8 X ( Z) ( X ) ( X Z) (Distributive law) 9 X X (DeMorgan s law) X X ( X ) Z X ( Z) X ( Z) ( X ) ( X Z) X X X X X X ( X ) X The left-hand side of the table describes the identities related to the OR operation, while the right hand side has the dual identities related to the ND operation. The duality means that in order to find the dual identity, one should change all ORs to NDs and vice versa and also change s to s and vice versa. Furthermore, we will see that proving any of the identities in the table can be used for proving the dual identity (replacing with and vice versa and s and s and vice versa and using dual rules when needed). Identities,2,5,6 and 8 follow Huntington rules. Let us prove identity 4 (for OR) using those identities

6 hapter : oolean lgebra 6 X X ( X X ) ( X X ) ( X X ) X ( X X ) X X We first used identity (for ND), then identity 2 (for OR), then the distributive law (identity 8) followed by identity 2 (for ND) and finally identity (for OR). In order to prove the dual identity, i.e., identity 4 for ND, we use the dual identities in the same order (i.e., replacing with and vice versa and s and s and vice versa and using dual rules when needed): X X ( X X ) ( X X ) ( X X ) X ( X X ) X X The proof of identity 3 (for OR) is: X ( X ) ( X X ) ( X ) X ( X ) X X The proof of identity (for OR) is: X X X X ( ) X ( ) X X X Let us now return to the example we had earlier: Prove: if α then means. Using DeMorgan s law we have ( ) α ( ) α ( ) α. We therefore see that if, we must have since otherwise, the right hand side of the equation will be..4) The Truth table truth table is a table describing all the combinations of the possible values of the variables in a oolean function. The truth table below describes all possible values of the variables of the function F where F f ( X, ) X X : X F X X

7 hapter : oolean lgebra 7 One can easily see that the right hand column describing the value of F for all possible combinations of the values of X and, is exactly the same as the left hand side column describing the variable X. This means that X equals that identity is true. Using truth table we can easily prove DeMorgan s laws: X X. This is another way to prove X X X X X.5) The order of operations s in regular math, we have a similar order of performing the logical operations. First evaluate the expressions in parenthesis. In evaluating an expression, first perform the NOTs then the NDs and then the ORs. When we have a NOT of an expression, we first evaluate the expression and then perform the NOT, i.e., as if we had parenthesis under the bar. For F ( ) where, and ( ) ( ) ( ) ( ) ( ). Then we calculate F ( )..6) The XOR operation, we first calculate. Then we calculate We define the Exclusive OR (XOR) operation as. This means that if., and denote it by What is the definition of XOR of n variables? If an odd number of them are s, the XOR is

8 hapter : oolean lgebra 8.7) anonic representation of oolean functions Let us describe the two anonic representations of a oolean function of three variables f (,, ) given by the following truth table: The 3 equations below also describe the same function: ( ) ( ) ( ) ( ) It is easy to see that each of the terms in the first equation matches one of the combinations of the variables that produce in. One can also see that the 2 nd equation is some simplification of the first one (which was simplified using some of the basic identities). The first two equations have the form of Sum Of Products (SOP). The third equation has the form of Products Of Sums (POS). Note that all the terms in the first equations are products of all the variables of f (,, ). Products that include all of the variables of a function are call Standard Products or Minterms. The anonic SOP representation of a function is a SOP in which all products are standard products. Therefore, the first equation is a anonic representation of, while the 2 nd is just a regular SOP representation.

9 hapter : oolean lgebra 9 One can use the laws (basic identities) to convert a SOP to the canonic SOP: The function F f (,, ) can be converted to its canonic representation by NDing each term with the missing variable OR its complement and the Distributive law: F ( ). n easier way is to look at the truth table and write down the terms that should be in F. In the truth table above, the function f (,, ) should be for the combination (,, ) (,,) therefore the canonic SOP must include the term which is iff (,, ) (,,). [This is the definition of ND: is only if and, and ]. sum that includes all of the variables of a function is called a Standard Sum or a Maxterm. The anonic POS representation of a function, is a POS in which all sums are standard sums. Therefore the third equation is the anonic POS of the function f (,, ). We can find the POS canonic representation of an equation by ORing each term with the missing variable ND its complement and the Distributive law: F ( ) ( ) ( ) gain, an easier way is to look at the truth table and write down the terms that should be in F. In the truth table above, the function f (,, ) should be for the combination (,, ) (,,) therefore the canonic POS must include the term, i.e., which is iff (,, ) (,,). [This is the definition of OR: is only if and, and, i.e.,. One May also use DeMorgan s law to see that i.e., if and only if (,, ) (,,), we have and therefore ]., Let us look again at the two canonic equations representing the same function given in the previous page: ( ) ( ) ( ) ( ) Suppose we know that the right hand side term of the SOP equation is, what is the value of the left-hand side term of the SOP equation? What is the value of the left-hand side term of the POS equation? The left hand side term of the SOP must be since if the term on the right hand side is, it means that the combination identified by this term is true. Therefore, any other combination, such as the one which should be identified by the left-hand side term cannot be true. Remember, each term identifies a distinct combination of the variables.

10 hapter : oolean lgebra The left-hand side term of the POS equation must be. This is so since we know for sure that, and so, all terms of the POS equation must be, otherwise we will have. Similarly, suppose we know that the right hand side term of the POS equation is, what is the value of the left-hand side term of the POS equation? What is the value of the left-hand side term of the SOP equation? The left-hand side term of the POS equation must be since again, each term identifies a distinct combination, and a certain combination has already been identified by the right hand side term. The difference between SOP and POS is that in SOP, a term that identifies a combination of the variables becomes, while in POS, a term identifying a combination becomes. The value of the left hand side term of the SOP equation must be since we know that which means that all terms in the SOP must be. For any combination of the variables only one of the 2 3 terms of the two canonic equations will identify the combination..8 Gates The basic building blocks which are used to implement a logic function are called gates. ny equation can be considered as a system having inputs (the variables) and outputs (the result of applying the functions on the variables). The equation f (,, ) describes a system having 3 inputs,, and a single output..8. n ND gate Its equation is. We draw it as in Figure.4. Its truth table is given below and is identical to the ND operation. Figure.4 n ND gate

11 hapter : oolean lgebra.8.2 n OR gate Its equation is. We draw it as in Figure.5. Its truth table is given below and is identical to the OR operation. Figure.5 n OR gate.8.3 NOT gate (usually called an INVERTER) Its equation is. We draw it as in Figure.6. Its truth table is given below and is identical to the NOT operation. Figure.6 n Inverter (a NOT gate).8.4 NND gate Its equation is. We draw it as in Figure.7. Its truth table is given below. Figure.7 NND gate

12 hapter : oolean lgebra NOR gate Its equation is. We draw it as in Figure.8. Its truth table is given below. Figure.8 NOR gate.8.6 XOR gate Its equation is. We draw it as in Figure.9. Its truth table is given below. Figure.9 XOR gate Figure. is a simple example of implementing a oolean function using gates. We here build a XOR gate, using ND, OR and NOT gates: Figure. uilding a XOR gate using ND, OR & NOT gates

13 hapter : oolean lgebra 3.9 Universal system Note that since the only operators we defined in oolean algebra are the ND, OR and NOT operators, it is clear that having these three kind of gates in our hands, enables us to build any desired function. Therefore, we call the set of ND, OR and NOT gates, a universal system. NND gate is itself a universal system and so it is called a Universal Gate. In order to show that we can build any desired function using only NND gates, we will show that we can implement all of the 3 operators ND, OR and NOT using only NND gates. Let us start with the NOT operation. We want to implement using a NND gate whose function is. If we choose to be or connect the input to the other input, we create an inverter since and also : or Figure. n inverter made of a NND gate Since a NND gate is just an ND gate which is followed by an inverter, all we need in order to convert it back to a regular ND gate, is to add one more inverter: Figure.2 n ND gate made of NND gates uilding the OR is a little bit more difficult. We need to use DeMorgan s laws:. Now, it is easy to implement the OR using 3 NND gates, two as inverters and the third one to perform the NND operation on the first two s outputs. Figure.3 n OR gate made out of NND gates

14 hapter : oolean lgebra 4 Let us now try to implement a XOR gate using only NND gates. The easiest way is to replace any inverter in Figure. with the inverter of Figure., and any ND gate with the ND gate of Figure.2, and finally, the OR gate with the OR of Figure.3: not and or We can reduce the gate count, if we delete the two redundant pairs of inverters. Those are redundant since Figure.4 uilding a XOR gate using only NND gates ( X ) X. Eventually we end with: Figure.5 XOR gate made of NND gates

15 hapter : oolean lgebra 5. Timing issues of gates Let us first define some terms. signal is a continuous function of the time t. logic level is a predefined voltage range that is recognized by a gate as a level. In the well-known TTL 74xx logic family, a level was defined as.v to.2v. logic level is another predefined voltage range that is recognized by a gate as a level. In the 74xx logic family, a level was defined as 2.v to 5.v. The signal has a logic level when the value of the signal in the range of logic level or in the range of logic level. signal is called stable at a time interval if it stays in the same logic level along the entire time interval. Let us explore the behavior of a simple gate. We input the signal (t) to an inverter and receive the signal (t) at the inverter s output. (t) (t) Figure.6 Naming the signals of a NOT gate The input signal (t) starts at so (t) is. t a certain point at time, i.e., at t, we change the input signal to be. The gate does not respond immediately. Its response is depicted in Figure.7 below. We see that it takes some time till the output signal changes. The time period in which the output signal still stays in the initial logic level, i.e., the time in which the gate does not response to the input change, is called the contamination delay and is denoted by t cd. The time required for the output to reach its final, i.e., stable level, is called the propagation delay and is denoted by t pd. These two time intervals are described in Figure.7 below for the rising and falling of the signals (t) and (t) where (t) is changing at t and t. When we implement a logical function using gates, we must consider the timing. When we want to know how soon will the output of a logical system be valid, i.e., in its stable logical level, we need to consider the worst case of all the gates. If this is a combinational system, we should take into account the sum of the delays of the maximum path between the input and the output signals. So, for our purposes, we can draw the signals as having valid logical values after the maximal t pd of the gates involved.

16 hapter : oolean lgebra 6 (t) t t t t ideal (t) t The actual (t) V Logic level V Logic level t cd t pd t cd t pd t (t) in digital levels t pd t t t pd t Figure.7 The timing behavior of a NOT gate In Figure.7, we see the input signal (t) at the top. The response of an ideal gate, i.e., without any delay, is described as ideal (t). The actual signal (t) at the output appears 2 nd from the bottom. For our analysis of digital circuits we can use the digital levels picture shown at the bottom of Figure.7.. Multiple inputs gates Now we know that gates have delays. We should take that into account when we build systems that are more complex then a single gate. In computer science, the analysis of an algorithm usually deals with its complexity or performance, expressed as the number of operations required,

17 hapter : oolean lgebra 7 and its cost in the memory units required. In analysis of hardware systems, we have similar measures. The performance is measured by the maximum delay of the system and the cost by the number of required gates. Let us now build an n inputs ND gate using two inputs ND gates only. The simplest way is based on induction. When we want to build a three input ND gate using two inputs ND gate we ll use the rules saying that ( ), i.e., we ll use one gate to produce and another gate to ND the result with. Using induction, we can quite easily build an n inputs ND gate, adding a single input at a time. This is depicted in Figure.8: I I I 2 I n-2 I n- Figure.8 uilding an n inputs ND gate using 2 inputs ND gates We will define such a structure recursively by describing an n inputs gate built of an (n-) input gate and a simple 2 inputs gate: I I I n-2 I n- Figure.9 uilding an n inputs ND recursively In this simple way, the cost of an n inputs ND gate is (n)n-, i.e., we need n- gates, 2 input ND gates, in order to build an n inputs ND gate. The delay is given by D(n)(n-)T where T is the delay of a single 2 inputs ND gate. The reason for this dependency of the delay on the number of inputs is the chaining of the gates. ecause of this structure, a change in the I should propagate through n- gated until it reaches, i.e., influences, the output. This seems a little exaggerated. There must be a better way. That way is to use binary tree structure. The depth of that tree will determine the maximal delay. This can be seen in Figure.2 below.

18 hapter : oolean lgebra 8 I I I 2 I 3 I 4 I 5 I 6 I 7 I n/2- I n-4 I n-3 I n-2 I n- Figure.2 uilding an n inputs ND gate using a tree of inputs ND gates

19 hapter : oolean lgebra 9 We can define such a structure recursively by describing an n inputs gate built of two n/2 input gates: I n/2 inputs I I n/2- I n/2 n/2 inputs I n/2 I n- Figure.2 recursive building of an n inputs ND gate The cost of such an n inputs gate stays (n)n-. This is so since it really does not matter how we add the inputs, since every new input forces us to add a single gate. It is quite clear from Figure.9 that the delay follows the recursive equations D ( n) D( n/ 2) T. This immediately means that the delay is logarithmic, i.e., D( n) T lg n. This is so since we can write: 2 D ( n) D( n / 2) T D( n / 4) T T D( n /8) T T T, etc., so we see that we have to sum lg n times the delay T. 2 When n is not an exact power of 2, there are several optional trees, all with depth of lg 2 n, to ( n) T lg n. arrange the gates. The delay in such case is given by D 2 We use basic gates of 2 inputs although in practice gates with more inputs are available. ( n) T lg n. Note that if we had a basic gate of 3 inputs we would get D 3

20 hapter : oolean lgebra 2.2 Decoders It is time now to get to our first useful system. We are going to build a Decoder. decoder has n inputs and 2 n outputs. Only one of its outputs is at a given time. The combination of the n input lines, each can be or, determines which of the outputs is on, i.e.,. s a matter of fact, the combination at the input represents a binary number in which the rightmost digit has a value (or weight) of, the next digit has a value of 2, the next has a value of 4 and the next of 8 and so on. Thus the combination has a value of and the combination has a value of 7 since We would like to build a decoder having only two inputs, I and I, forming together a two bit number [I, I ] which can have the values,,2 or 3. nd so, the decoder has 4 outputs,, 2, and 3. We would like the i-th output to be when the input has the combination that represent the number i. How do we do that? We use a truth table to describe the decoder and then find the equations of the outputs from that table; [I I ] 2 3 We immediately see that the equations of the outputs are given by: I I I I I I 2 I I 3 So the decoder can be built as described in Figure.22 below:

21 hapter : oolean lgebra 2 I I 2 3 Figure.22 2 inputs 4 outputs decoder We would like to recursively build an n inputs decoder using (n-) inputs decoders. The next figure shows how this is done: I - I n-2 n- Decoder # (n-) 2 (n-) 2 2 n- outputs 2 n- - 2 n- 2 n outputs Decoder #2 (n-) 2 (n-) 2 n- 2 n- outputs I n- 2 n - Figure.23 Recursive Decoder

22 hapter : oolean lgebra 22 The idea here is that whenever the new input, I n-, is only the outputs of the upper decoder are enabled. Thus, one of them, which is determined by the combination of the inputs I -I n-2, will be. The lower decoder has a in the parallel output, but since all its outputs are disabled when I n- is, the lower outputs are all. When I n- is, the situation is reversed. The lower decoder outputs are enabled and the upper decoder outputs are disabled, so we will have in the appropriate output of the lower decoder only. We could see that through the truth table. The truth table of a single decoder is : I n-2 I 2 n When we have two decoders but without the additional ND gates we would have the following truth table: I n- I n-2 I 2 n- - 2 n n -

23 hapter : oolean lgebra 23 With the ND gates, we make sure that the upper right hand side of the table is filled with zeros, i.e., the outputs of the lower decoder are all disabled when I n-. We also make sure that the lower left hand side of the table is filled with zeros, i.e., the outputs of the upper decoder are all disabled when I n-. nd so we get the final truth table of: I n- I n-2 I 2 n- - 2 n Eventually we got a truth table in which only the main diagonal has s and the rest is filled with s, which is exactly what is expected from a decoder. The decoder manufacturers are aware of the need of such an expansion so they add an enable input to their decoders: 2 n - I I 2 3 Figure.24 decoder with an Enable input E

24 hapter : oolean lgebra 24 This makes it simple to expand the decoder. In most cases the manufacturer adds several enable inputs, some with inverse polarity, so no glue logic is required when two such decoders are used. I I 2 3 E 3 E 2 E Figure.25 decoder with several Enable inputs This is the case when we deal with discrete components. When we design a VLSI chip, we want to get rid of all redundant parts. nother look at Figure.23 reveals that the two decoders produce similar outputs. Therefore, a better design is to use a single decoder and duplicate its output as shown in Figure.26. I - I n-2 n- (n-) 2 (n-) Decoder 2 2 n- outputs 2 n- - 2 n- 2 n outputs 2 n- 2 n- outputs I n- 2 n - Figure.26 Recursive Decoder

25 hapter : oolean lgebra 25 In Figure.27 we show the recursion for a 3 8 decoder built that way: I 2 I I 2 7 Figure.27 complete 3 8 recursive decoder It is quite easy to see that the delay of such a decoder is given by D(n)D(n-)T where T is the delay of a single gate. This means that we have D(n)n٠T. Note that this structure is similar to the first way in which we built an n input ND gate (Figures.8 and.9). We can use a "tree style" approach to get a logarithmic delay. Try to do that as a homework exercise. The cost of the system in Figure.26, is n inverters and much more ND gates so we just count the ND gates as the cost. Since we see that the cost follows the recursive equation (n) 2 2 n- (n-) 2 n (n-), we have a geometric sequence with q2. Since (), (2)4, we have (n) n 2 n 4. There are two more issues in designing such systems that we did not consider. One is the length of the lines, i.e., the connecting wires. This has to do with the area of silicon that is required in

26 hapter : oolean lgebra 26 order to implement the design on silicon. We will not discuss that issue. The other thing is the Fan out of the gates. The gates are electronic devices which output and input currents. Since the output current of a gate is limited, it can drive only a limited number of gates. The number of gate inputs that can be driven by the output of a gate is called the Fan out of that gate. typical value of the Fan out is to 2. We would like to analyze a much severe case where the fan out of a gate is only 2. (Less then 2 means that we can connect the output of a gate only to a single input. This is too restrictive.) In our decoder, we see that each ND gate drives two other gates, so there is no problem there. However, the inverters drive 2 n- inputs, i.e., the number of the inputs that should be driven by the inverters is exponential! How can we overcome such a problem when the allowed fan out is only two? The answer is that we should build a tree of inverters to produce 2 n- inverted outputs and 2 n- non-inverted outputs from the I n- input: I n- I n- I n- Figure.28 fan out expansion tree Note that since the depth of such a tree is about n, we almost did not increase the delay of the decoder.

27 hapter : oolean lgebra 27.3 Multiplexers multiplexer (Mux), as a decoder, is one of the basic devices used in building computers. n n m multiplexer, n>m, is a device with n inputs and m outputs. It also has some select inputs that determine which of the inputs are transferred to the outputs..3. simple mux We first define the simplest multiplexer which is a 2 multiplexer. It has two data inputs and (or I and I ) and one data output,. It also has a single select input denoted by S. Its drawing and function is given in Figure.29. (or I ) 2 (or I ) S Figure.29a The schematic drawing of 2 multiplexer (or I ) (or I ) S Figure.29b 2 mux selects between the 2 inputs s shown in Figure.29b, the multiplexer functions as a switch. The S input determines which of the two inputs is connected to the output. When S, we have (or I ). When S, we have (or I ). The function of the mux can be written as: if S if S

28 hapter : oolean lgebra 28 The truth table is therefore: S (I ) (I ) The logic function of a mux is very simple: S S (or if we use the other notation: I S I S ). The implementation using gates is also simple: (or I ) (or I ) S Figure.3 The inside of 2 multiplexer

29 hapter : oolean lgebra First expansion: 2n n mux, also called n*(2 ) mux The 2n n mux has 2n inputs and n outputs as shown in Figure.3. The data inputs represent two n bit numbers and the S input determines which of them is transferred to the n outputs. We denote the inputs by [n-:][ n-, n-2,, ], the inputs by [n-:][ n-, n-2,, ], and the data outputs, by [n-:][ n-, n-2,, ]. [n-:] [n-:] n n n*(2 ) n [n-:] S Figure.3 The schematic drawing of an n*( 2 ) multiplexor The function of the mux can is given by: [n-:] [n-:] if S [n-:] if S This can be implemented using n regular 2 muxes, i.e., the i, i and the i are connected to a single 2 mux. So, now we understand why we called that mux an n*(2 ) mux. In Figure.32 we see the internal structure of a 3*(2 ) mux S Figure.32 The inside of a 3*( 2 ) mux

30 hapter : oolean lgebra Second expansion: 2 k mux The 2 k n mux has 2 k inputs and a single output as shown in Figure.3. There are also k select inputs denoted S[k-:][S k-,s k-2,,s,s ]. There are 2 k combinations to the select lines. When S[k-:]i, i.e., the combination of [S k-,,s ] represents the number i, the i-th input is transferred to the output. Since there are 2 k inputs we have chosen to denote those inputs by I, I,, I 2 k -. I I 2 k I 2 k - k S[k-:] Figure.33 The schematic drawing of a 2 k multiplexor We would like to build an 8 (i.e., a 2 3 ) mux using 2 muxes of 4. This is pretty easy. We have to add another select input, S 2, to the two select inputs, S and S, of the 4 muxes (i.e., 2 2 muxes). This S 2 input will choose between the two outputs of the two 4 muxes. See Figure.34. I I I 2 I 3 4 S S 2 The number represented by S[k-:] is the serial number of the input transferred to the output. I 4 I 5 I 6 I 7 4 S S S 2 S 2 S S Figure mux build of two 2 2 muxes

31 hapter : oolean lgebra 3 Since adding a select line exactly doubles the number of combinations, we can similarly build a 2 k mux using two 2 k- muxes and a single 2 mux. Thus, we can build a 2 k mux recursively. In Figure.35 we see the recursive definition of such a mux. I 2 k- inputs I 2 k- I 2 k- - k- 2 2 k- inputs k- I 2 k- I 2 2 k- I 2 k - k- k- S k-2,,s S k- Figure.35 uilding a mux recursively The cost equation is ( k) 2٠(k-) (). This means that the cost is actually: (k) ()٠[ 24 2 k- ] ()٠(2 k -). Note that here we look at k instead of n where n is the number of the inputs and follows n2 k. So (n) 2 ٠(n-). The delay equation is D( k) D(k-) D(). This means that the delay is given by D(k) k٠d() or D(n) lg 2 n٠ D 2. In Figure.36 we show the entire tree of an 8 mux.

32 hapter : oolean lgebra 32 I 2 I 2 I 2 2 I 3 2 I 4 2 I 5 2 I 6 2 I 7 S S S 2 Figure.36 The entire recursion depth in an 8 mux

33 hapter : oolean lgebra Third expansion: n n*( 2 k ) mux The n*(2 k ) mux has 2 k inputs, n bits each, i.e., each input represent an n bits binary number, and a single n bits output as shown in Figure.37. There are also k select inputs denoted S[k- :][S k-,s k-2,,s,s ]. There are 2 k combinations to the select lines. When S[k-:]i, the i-th input is transferred to the output. Since there are 2 k inputs we have choose to denote those inputs by I, I,, I 2 k -, sometimes denoted,,,z. I [n-:] (or [n-:]) I [n-:] (or [n-:]) n n n*(2 k ) n [n-:] I 2 k - [n-:] (or Z[n-:]) n k S k-,,s Figure.37 The schematic drawing of an n*(2 k ) multiplexer Similarly to the first expansion, the n*(2 k ) mux is built of n muxes of 2 k, each of them takes care for one of the n bits. n example of a 2 3 mux, i.e., a 3*(2 2 ) mux, is given in Figure.38 below.

34 hapter : oolean lgebra 34 2 D 2 2 D 2 D 2 D D D 2 S S Figure.38 The inside of a 3*( 2 2 ) mux We can also take apart the 4 muxes, which, as we already know, are built of 2 muxes:

35 hapter : oolean lgebra 35 2 D 2 2 D 2 D 2 D D D 2 S S Figure.39 The inside of a 3*( 2 2 ) mux in detail Figure.4 below shows the entire muxes family:

36 hapter : oolean lgebra 36 (or I ) 2 (or I ) S I I 2nd expansion: binary tree for 2 k 2 k [n-:] n First expansion: N bits in parallel n*(2 ) n [n-:] I 2 k - [n-:] n k S S[k-:] 3rd expansion: 2 k inputs of N bits in I [n-:] (or [n-:]) I [n-:] (or [n-:]) n n n*(2 k ) n [n-:] I 2 k - [n-:] (or Z[n-:]) n k S k-,,s Figure.4 The entire multiplexers family

37 hapter : oolean lgebra 37 We have only one last thing to say about muxes and decoders. They complement each other. mux is the inverse of a decoder. To show that, we will change our interpretation of decoders. Let us look at a 2 4 decoder that has an enable input denoted E. If E all outputs of the decoder are. If E, then the output selected by the code, or combination, of the inputs is. So, one can see the decoder as a switch controlled by the inputs that transfers the E data into one of the output as in Figure.4. I I 2 decoder 2 E E 2 I[:][I,I ] Figure.4 decoder as a controlled switch We can use Muxes and Decoders to multiplex multiple data streams on a single line as in Figure.42. This is called TDM, Time Division Multiplexing, since when we sequentially change the selection code S[:] 2 3 etc., we have a different data stream appearing on the line at different times. Note that the rate of switching the select lines should be 4 times higher than the rate in which the data streams may change. I I E I 2 2 I S,S Figure.42 4 data lines sharing a single line Suggested homework: ) recursive comparator 2) "LT" detector 3) tree decoder

38 hapter : oolean lgebra 38.4 Karnaugh maps In the last part of the oolean lgebra chapter, we demonstrate a simple technique used to simplify Sum Of Products representation of oolean functions. We first start with functions of 3 variables..4. Karnaugh maps of 3 variables Let us look at the following function : It is equivalent to the function: 2 2 This is so since ( ). Whenever we find two products terms that differ only in an inverted a single component, i.e., an input variable, we can erase that variable from the expression and reduce the number of sums by one. It would have been nice if we could spot pairs of product terms that differ only in one variable. In the truth table of, we see that the pair of and are not close to each other: We numbered the product by 5 and the product by. We see that they are far away from each other. The product numbered 6, which is also one of the products in, is close in the truth table to the one numbered 5, but these two, and, have two variables different in polarity, i.e., and have both different polarities in these two products. Let us define a measure of distance between two products. The Hamming Distance of two strings of bits, or two product terms, is the number of the bits that are different, i.e., the number of

39 hapter : oolean lgebra 39 variables in the product terms that have different polarity. Thus, the Hamming distance between product terms # and #5 is, while the Hamming distance between product terms #5 and #6 is 2. Let us now try to build another representation, instead of the truth table, similar to the truth table, but with a Hamming distance between its location. We draw the following two dimensional map, where the top row has all combinations in which and the bottom row has all combinations in which (this makes sure that the Hamming distance between 2 vertical locations is ):, Figure.43 Starting to fill the map We now have to select a way to fill the map with combinations according to their Hamming distance. Let us start with the combination, which represents. We choose this combination to be at the top left square of the map., Figure.44 The next step of filling the

40 hapter : oolean lgebra 4 The square to the right of that one, should differ from that combination only in one bit. So the possible combinations, taking into account in the top row is, are or. We choose, i.e., the combination is as in figure.45:, Figure.45 The next step of filling the map This choice, automatically determines the next two squares of the top line, since the one close to it can only be (only one bit is allowed to change, and we already have the combination, so we can only change from to ), and the last one can only be (again, only one bit is allowed to change). So eventually we get the following map, which is called a Karnaugh map:, Figure.46 Karnaugh map of 3 variables Let us now fill the Karnaugh map with s and s according to the function, similarly to the way we fill a truth-table:

41 hapter : oolean lgebra 4, Figure.47 Karnaugh map of the function Since we built the map in such a way that two adjacent squares have a hamming distance of, we can unite any two adjacent s, i.e., any two adjacent product terms, into a single product term having less variables in it. We should erase the variable that is different between the two product terms represented by the s. In our case, we have ones in product terms and 5, marked by the blue loop in Figure.47 above. Since we see that the bit that is different between these two locations is, while and stay the same, we conclude that the blue loop is represented by the product term of. The red circle, means that the product term numbered 6 stays without a change, since we do not have any other product term which is different only in a single variable. If we had such a product term, it would have been adjacent to that. We can use this method to simplify SOPs. Since when we move to the right, or to the left or up or down, only bit is changing, then any two adjacent s in these directions (not diagonally!) can be united. Let us see some examples: The Karnaugh map of another function is: 3, Figure.48 Karnaugh map of another function

42 hapter : oolean lgebra 42 We can cover all the s in the map in a very similar manner to the previous example:, Figure.49 The Karnaugh map of 3 Which results with 3. However, there is a better way, depicted in Figure.5 below:, Figure.5 better choice of loops for 3 ccording to our rules the blue loop stands for the product term, while the red one stands for the product term since in these two locations in the map, only is changing and and are s. So, in this example we have: 3. Our conclusion is therefore, that we should cover all the s in the map using as large loops as possible, since a larger loop means less variables in the product term representing the loop.

43 hapter : oolean lgebra 43 Note that we could have find that using the oolean lgebra rules, but we had to invest some effort, while using the Karnaugh Map, the chore is much simpler: ) ( ) ( ] [ ] [ 3 So the Karnaugh map technique is meant to ease the chore of simplifying SOPs. Let s look at another example: The blue loop represents the product term of, the red loop represents, and the dotted green loop represents the term. So, we can conclude that 4. However ) ( ) ( ) ( 4 careful look at the map reveals the reason. The blue and red loops cover all the cases in which. dding more loops, e.g., the green dotted one, means adding more unnecessary, i.e., redundant, product terms. So, from now and on we should try to find the minimal number of loops required to cover all the s in the map. Figure.5 The map of another function, 4,

44 hapter : oolean lgebra 44 Let us consider the following example: 5 It is easy to see that we have all combinations of and multiplied by (i.e., NDed with ) and so we can write: 5 ( ) [ ( ) ( ) ( ) ( )] Let us look at the map. These 4 locations having all possible combinations of and form a square:, We conclude from that example, that any rectangle of 2 n x 2 m s, covering all 2 n x2 m possible combinations of nm variables, means that we can erase those nm variables from the group of product terms in that rectangle, leaving only the rest of the variables. In our example, we have a 2 x 2 rectangle which means that we should erase 2 variables. We see that and are changing, and only stays the same for all the s in the rectangle. This means that the blue loop represents and so we have 5. nother example is the following case: Figure.52 The Karnaugh map of 5, Figure.53 Periodicity of Karnaugh map

45 hapter : oolean lgebra 45 If we look carefully at the map, we see the Hamming distance of a square at the right hand side column from a suaqre in the left hand side column, in the same row, is also. So, we these two squares are adjacent and we can unite them in case both have s. It is as if the map is folded or periodic. The same exact thing happens with more than row:, Figure.54 Periodicity of a column in Karnaugh map So here are the final rules: over all of the s in the map, with the minimal number of rectangle loops which will be as large as possible. The reasons are simple: l the s Otherwise we won t get the same function! Minimal number of loops- So we ll have the minimal number of product terms. s large as possible rectangle loops- The larger the rectangle, more variables are erased from the product term..4.2 Karnaugh maps of 4 variables Let us now deal with the case of 4 variables. It is very similar to the 3 variables case. We start with a map having 4x4 squares forming the required 6 combinations of 4 variables (62 4 ). Since now we have 4 rows, each row here is identified by two variables. Let us discuss the case where f (,,, D). We arbitrary choose and to identify the rows. gain we choose ٠ to be along the first row. The combination of the 2 nd row, as in the three variables map, should differ by one bit only from the first row, so it could be either or. We chose it to be

46 hapter : oolean lgebra 46 arbitrarily. The next two rows automatically should get the combinations of and. In a similar manner to that and to the way we chose the combination of the columns in the three variables map, we assign combinations to the columns, each differs from the previous one by one bit. Eventually we get the following map: D Figure.55 Karnaugh map of 4 variables Note that if we had chosen a different assignment of the variables to the map locations, the result of the simplification will still be the same. This is so since when two product terms are different in a single variable, they will still be adjacent in the new arrangement and therefore, the simplification, which unites these two adjacent s will give the same result.

47 hapter : oolean lgebra 47 Let us give a single example: D D D D D Figure.56 Karnaugh map of 4 variables function Which, according to the loops is equal to: D Note: In 4 variables, there are cases in which several solutions are possible. We ll see that in the coming section..4.3 Don t care cases in Karnaugh map Let us build a D to 7 Segments decoder. 7 segment display, is a display device having 7 light emitting segments that is capable of displaying the digits 9 by lighting some of the segments according to the required digit. Figure.57 below demonstrates the seven segments and the digits that can be displayed. Figure.57 Forming the digits -9 using a seven segments display device

48 hapter : oolean lgebra 48 Let us now look at the decoder that translated a 4 digits code, representing a binary number, into the seven segments. This decoder is called a D to Seven Segments decoder, since we use inary oded Decimal digit as the input for the decoder: S I I I 2 I 3 D to 7-Seg. decodrer S 2 S 3 S 4 S 5 S 6 S 7 The decoder s truth-table is: Figure.58 The connections of a D to 7 Segments decoder The digit I 3 I 2 I I S S 2 S 3 S 4 S 5 S 6 S

49 hapter : oolean lgebra 49 The truth-table was filled as in the following example: In the 2 nd line of the table, [I 3,I 2,I,I ], which means the digit should be displayed. nd so, only S 3 and S 6 should be on, i.e., s thus forming the digit as in Figure.57. We apply the technique of Karnaugh map to find the simplified equation of S : I 3 I 2 I I S Figure.59 The Karnaugh map of S I I I I I I I I I I I I which results with: There are more possible solutions with identical number of product terms of identical sizes: I 3 I 2 I I Figure.6 The Karnaugh map of S, another possibility of loops

50 hapter : oolean lgebra 5 S I I I I I I I I I I I I which results with: or I 3 I 2 I I Figure.6 The Karnaugh map of S, a third possibility of loops S I I I I I I I I I I I I which results with: These solutions are not the optimal solution for the D to 7 segments decoder. The reason for that is that we can do better if we take into account the fact that the combinations of [I 3 I 2 I I ],, 2, 3,4 or 5 will never happen! Thus, we actually do not care what is the result of S for these input combinations. In such a combination, we can choose S to be either or (but we have to choose one of them). We call such cases Don t care cases and denote them in the truth table or the Karnaugh map by Ф, which stands for or. So, the truth-table is now:

51 hapter : oolean lgebra 5 The digit I 3 I 2 I I S S 2 S 3 S 4 S 5 S 6 S Ф Ф Ф Ф Ф Ф Ф Ф Ф Ф Ф Ф Ф Ф 2 Ф Ф Ф Ф Ф Ф Ф 3 Ф Ф Ф Ф Ф Ф Ф 4 Ф Ф Ф Ф Ф Ф Ф 5 Ф Ф Ф Ф Ф Ф Ф and the Karnaugh map of S is therefore I 3 I 2 I I Ф 2 Ф 3 Ф Ф 5 4 Ф Ф 8 9 Figure.62 The Karnaugh map of S with Don t are cases

52 hapter : oolean lgebra 52 We can set any of the don t care cases to be or as we please, and then draw the loops. It seems that we can reduce the product terms to a minimum if we choose all of the don t care cases to be used as s. So we have: I 3 I 2 I I I I 3 2 I 2 I I 2 I Ф Ф Ф Ф I Ф Ф 8 9 Figure.63 The Karnaugh map of S, using the Don t ares as s S I I I I I I I which results with:. This is definitely simpler to implement, i.e., less gates, compared to the previous results. gain, there may be more possibilities. In our specific case, we have another solution depicted in Figure.64 below.

53 hapter : oolean lgebra 53 I 3 I 2 I I Ф 2 Ф 3 Ф Ф 5 4 Ф Ф 8 9 Figure.64 The Karnaugh map of S, using the Don t ares as s S I I I I I I I which results with: which has the same complexity as the other solution. We can draw Karnaugh maps of 5 and 6 variables. Those are 3 dimensional maps. More variables result with more than 3 dimensions. t this point, we know enough about oolean lgebra, gates and equations, so we can design all kinds of desired systems. We will use our ability to design arithmetic units after learning about computer arithmetic in the next chapter.