A B D 1 Y D 2 D 3. Truth table for 4 to 1 MUX: A B Y 0 0 D D D D 3

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1 . What is a multiplexer? esign a 4 to multiplexer using logic gates. Write the truth table and explain its working principle. Answer: is a circuit with many inputs but only one output. esigning of 4 to multiplexer shown below: A B Y 2 3 Truth table for 4 to MUX: A B Y 2 3 Working principle of 4 to multiplexer: From the above diagram, the Logic Equation for 4 to multiplexer is Y A B A B AB AB 2 3 If A, B then, Y Similarly, if A= and B= then Y=, if A= and B= then Y= 2 and, if A= and B= then Y= 3 Page:

2 2. onstruct 4: multiplexer using only 2: multiplexer. Answer: Logic Equation for 2 : is Y A A Logic equation for 4 : Multplexer is Y A B A B AB AB Y A ( B B ) A( B B ) We require three 2: s and the connection is shown below. B 2: A B 2: Y 2 3 2: 3. onstruct 8: multiplexer using only 2: multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 8 : is Y A B A B A B A B AB AB AB AB Y A ( B B B B ) A( B B B B ) Y A [ B ( ) B( 2 3 )] A[ B ( 4 5 ) B( 6 7 )] Page: 2

3 2: B 2: 2 3 2: A 2: Y 4 5 2: B 2: 6 7 2: 4. esign 6 to multiplexer using 8 to multiplexer and one 2 to multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 8: is Y A B A B A B A B AB AB AB AB Logic Equation for 6 : is Y A B A B... A B A B AB AB... AB AB Y A ( B B... B B ) A( B B... B B ) Page: 3

4 B 8: A 7 B 2: Y 8 5 8: 5. esign 32 to multiplexer using 6 to multiplexer and one 2 to multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 6 : is Y A B A B... AB AB 4 5 Logic Equation for 32 : is Y A B E... A BE A BE AB E... ABE ABE Y A ( B E... BE BE ) A( B E... BE BE ) B E : A 5 B E 2: Y 6 3 6: Page: 4

5 6. Mention the differences between decoder and demultiplexer. Answer: emultiplexer There is one data input and multiple output. There are selects used as control bits. The data input appears at one of the output as per the control inputs. Input appears at the output where subscription of the output is equal to the decimal equivalent to the inputs. ecoder There is no data input. The only inputs are the control bit. One of the output is high as per the control inputs. Output becomes high where subscription of the output is equal to the decimal equivalent to the inputs 7. (a) Realize Y A B B AB using an 8 to. (b) an it be realized with a 4 to multiplxer? Answer : ( a) Logic Equation for 8: is Y A B A B A B A B AB AB AB AB We should express Y as a function of three variables i.e function of minterms. Y A B B AB Y A B( ) B ( A A ) AB Y A B A B AB A B AB Y A B A B A B AB AB omparing with the Logic equation of 8:, we have and A B = = 2 = 3 = 4 = 5 = 6 = 7 = 8: Y ( b) Y A B B AB Y A B B ( A A ) AB Y A B AB A B AB Y A B. A B. AB. AB. Logic equation for 4 : Multplexer is Y A B A B AB AB 2 3 Page: 5

6 We have,,, and 2 3 A B =ʹ = 2 =ʹ 4: Y 3 = 8. Implement the following Boolean functions using 4: multiplexer (MUX): ( i) Y f ( A, B,, ) m(,,2, 4,6,9,2,4) ( ii) F( A, B, ) m(,3,5,6) Answer: Logic equation for 4 : Multplexer is Y A B A B AB 2 AB3 Y f ( A, B,, ) m(,,2,4,6,9,2,4) Y A B A B A B A B A B AB AB AB Y A B ( ) A B( ) AB AB( ) omparing with Logic Equation of 4 :, We have Page: 6

7 I = I = I 2 = I 3 = 4: I 4 = I 5 = I 6 = I 7 = 4: A B 4: Y I 8 = I 9 = I = I = 4: 2 I 2 = I 3 = I 4 = 4: 3 I 5 = Logic equation for 4 : Multplexer is Y A B A B AB AB (ii) 2 3 F( A, B, ) m(,3,5,6) F A B A B AB AB F A B. A B. AB. AB. omparing with Logic Equation of 4 :, we have,, and 2 3 Page: 7

8 A B = = 2 = 3 =ʹ 4: F 9. Implement the Boolean function expressed by SOP: f ( A, B,, ) m(, 2,5,6,9,2) using 8 to MUX. Answer: AB = = f d d' d' d' d' d 8: MUX data input = = ' 2 = 3 =' 4 = 5 = 6 = ' 7 = ircuit diagram: A B ' : MUX f Page: 8

9 . Implement the Boolean function: F( A, B,, ) m(,,2, 4,5,7,8,9) using 8 to multiplexers. raw the logic diagram and explain the operation. Additional gates can be used if required. Answer : ( a) Logic Equation for 8: is Y A B A B A B A B AB AB AB AB Logic Equation for 2 : is Y A A F( A, B,, ) m(,,2,4,5,7,8,9) F A B A B A B A B A B A B AB AB F A ( B B B B B B) A( B B ) omparing with 2 : Logic Equation, we have B B B B B B B. B. B. B. B. B. B. B. B B B. B. B. B. B. B. B. B. B I = I = I 2 = I 3 = I 4 = I 5 = I 6 = I 7 = 8: Multiplxer Aʹ B F I 8 = I 9 = I = I = I 2 = I 3 = I 4 = I 5 = 8: Multiplxer (Note: 9 and are similar. But method for 9 is preferable) A Page: 9

10 . Realize the following Boolean function: P f ( w, x, y, z) (,,5,6,7,,5) using (i) 6: MUX (ii) 8: MUX (iii) 4: MUX Answer : ( i) Logic Equation for 6 : is P w x y z. w x y z. w x yz. w x yz. w xy z. w xy z. w xyz. w xyz. wx y z wx y z. 9 wx yz. wx yz. wxy z. 2 wxy z. 3 wxyz. 4 wxyz. 5 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w x y z. w x y z. w x yz. w x yz. w xy z. w xy z. w xyz. w xyz. wx y z. + wx y z. wx yz. wx yz. wxy z. wxy z. wxyz. wxyz. omparing with Logic Equation for 6 :, we have and w x y z = = 2 = 3 = 4 = 5 = 6 = 7 = 8 = 9 = = = 2 = 3 = 4 = 5 = 6: P ( ii) Logic Equation for 8: is Y x y z. I x y z. I x yz. I x yz. I xy z. I xy z. I xyz. I xyz. I Logic Equation for 2 : is Y w w Page:

11 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w ( x y z x y z xy z xyz xyz) w( x yz xyz) P w ( x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz.) w( x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz.) omparing with Logic Equation of 2:, we have x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz. x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz. x y z I = I = I 2 = I 3 = I 4 = I 5 = I 6 = I 7 = 8: Multiplxer wʹ x y z P I 8 = I 9 = I = I = I 2 = I 3 = I 4 = I 5 = 8: Multiplxer w Page:

12 (iii) Logic equation for 4 : Multplexer is Y w x w x wx 2 wx3 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w x ( y z y z) w x( y z yz yz) wx yz wxyz omparing with Logic Equation for 4:, we have y z y z 2 3 y z. y z. yz. yz. y z yz yz y z. y z. yz. yz. yz y z. y z. yz. yz. yz y z. y z. yz. yz. y z I = I = I 2 = I 3 = 4: y z I 4 = I 5 = I 6 = I 7 = 4: y z w x 4: P I 8 = I 9 = I = I = 4: 2 y z I 2 = I 3 = I 4 = 4: 3 I 5 = Page: 2

13 2. esign and implement B to excess-3 code converter using four 8: multiplexers. Take MSB A as map entered variable(input variable) B lines as select lines, assuming f(a,b,,) as B input. Answer: Truth table for converting B to Excess-3 B Excess-3 A B W X Y Z esigning of the multiplexer whose output is W B A= A= X X X X X X W A A 8: MUX ata Input =A =A 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is X B A= A= X X X X X X X 8: MUX ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is Y B A= A= X X X X X X Y 8: MUX ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is Z B A= A= X X X X X X Z ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = Page: 3

14 Page: B B B B W X Y Z A A 8: 8: 8: 8:

15 3. Realize a logic circuit for octal to binary encoder. Answer: Truth table for octal to binary encoder Input Output B 2 B B B 2 B B 4. Implement a full adder using a 3 to 8 decoder. Answer: Truth table for full adder A B Sum arry Page: 5

16 A B 3:8 ecoder Sum 5 6 arry 7 5. Implement full adder using I 7438 Answer: Truth table for full adder A B Sum arry A B 3:8 ecoder Sum 5 6 arry 7 Page: 6

17 6. Implement 3 bit binary to gray code conversion by using I Answer: Truth table for converting 3 bit binary to gray code Binary code Gray code A B X Y Y K-Map for X: K-Map for Y: K-Map for Z: AB AB AB X=A Y=AB+AB Z=B+B A X B 7439 Y 7439 Z Page: 7

18 7. esign a priority encoder for a system with a 3 inputs, the middle bit with highest priority encoding to, the MSB with the next priority encoding to, while the LSB with least priority encoding to. Answer: Truth table of the priority encoder Input Output A B X Y AB K-Map for X: AB K-Map for Y: X=A+B Y=AB+B=B(A+) A B X Y Page: 8

19 8. esign a 4 to 6 line decoder using 2 to 4 line decoder which has the active low outputs as active low enable input. Explain its operation. Answer: 2 to 4 line decoder E A B 2 to 4 line decoder 2 to 4 line decoder E 2 to 4 line decoder E 2 to 4 line decoder E 9. Write the comparisons between PLA and PAL. Answer: PAL The output OR-gate array is fixed while the input AN gate array is fusible linked and thus programmable. PAL is easier to program. PAL is less expensive. PLA Both output OR-gate array and input AN gate array are fusible linked. PLA is more complicated since the number fusible links are more compared to PAL PLA is more expensive compared to PAL. Page: 9

20 2. esign 7-segments decoder using PLA. Answer: Seven segment indicator: a f b g e c d Following table shows the segments should light up to display a number. Number to display Segments to light up a,b,c,d,e,f b,c 2 a,b,d,e,g 3 a,b,c.d,g 4 b,c,f,g 5 a,c,d,f 6 a,c,d,e,f,g 7 a,b,c 8 a,b,c,d,e,f,g 9 a,b,c,f,g Page: 2

21 Page: a b c d e f g A B

22 2. Implement the following function using PLA: A(x,y,z)=Σm(,2,3,6); B(x,y,z)=Σm(,,6,7); (x,y,z)=σm(2,6) Answer: A B A(x,y,z) =Σm(,2,3,6) B(x,y,z) =Σm(,,6,7) A(x,y,z) =Σm(,2,6) Page: 22

23 22. raw the PLA circuit and realize the Boolean functions: X A B AB B, Y A B AB, Z B Answer : X A B AB B A B AB B ( A A ) A B AB AB Y A B AB Z B B ( A A ) AB A B A B Y Z Page: 23

24 23. escribe the working principle of 3:8 decoder. esign a circuit that realizes the following functions using a 3:8 decoder and multi input OR gates. ( i) F ( A, B, ) m(,3,7) (ii) F ( A, B, ) m(2,3,5) 2 Answer: Working principle of 3:8 decoder: There are 3 inputs and 8 outputs in a 3:8 decoder. One of the output is HIGH and remaining seven are LOW according to inputs. This is shown in truth table. A B 3:8 ecoder Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 AB AB AB AB AB AB AB AB Truth table of 3:8 ecoder : A B Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Page: 24

25 A B 3:8 ecoder Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 AB AB AB AB AB AB AB AB F (A,B,) =Σm(,3.7) F 2 (A,B,) =Σm(2,3.5) 24. What is magnitude comparator? esign one bit comparator and write the truth table, logic circuit using basic gates. Answer: A magnitude comparator compares two binary numbers and it produces an output showing the comparison of the two input numbers. For example, two n-bit binary numbers X=X X..X n and Y=Y Y Y n are compared. There are three ouputs. The outputs are for X>Y, X=Y and X<Y as shown in the figure below. Page: 25

26 X X n Y Y n n-bit comparator X>Y X=Y X<Y esigning of one bit comparator: Truth table Input Output X Y X>Y X=Y X<Y If G, L, E stand for greater than, less than and equal to respectively, then (X>Y): G=XYʹ; (X<Y):L=XʹY; (X=Y): E=XʹYʹ+XY=(XYʹ+XʹY)ʹ=(G+L)ʹ X X<Y X=Y Y X>Y Page: 26

27 25. What is parity generator? Explain with an example. Answer: A parity generator is a logic circuit which produces either even parity number or odd parity number as per requirement. For example: X 7 X 6 X 5 X 4 X 3 X 2 X X X 8 ata Input 9-bit number with odd parity Page: 27

28 26. What is parity checker? Explain with example. Answer: A parity checker check the parity of a number whether the number is of even parity or odd parity. For example: The exclusive OR gate produces an output when the input ( X X 7 ) is of odd parity and produces when the input is of even parity. X 7 X 6 X 5 X 4 X 3 X 2 X X Y Page: 28

29 27. Give state transition diagram of SR,, JK and T flip flops. Answer: S R State Transition iagram S R S R S R flip flop SR flip flop J K J K J K T J K T T flip flop JK flip flop T T Page: 29

30 28. Obtain the characteristic equation of SR, JK, and T flip flops. Answer: S R State Transition iagram S R S R S R flip flop SR flip flop J K J K J K T J K T T flip flop JK flip flop T T Excitation Table for SR, JK, and T flip flop is given below is prepared State Transition iagram above n n+ S R J K T X X X X X X Page: 3

31 From the Excitation Table, K-map is formed and then the characteristic equation is determined. SR n x haracteristic Equation for SR flip flop is x n+ =S+R n JK n haracteristic Equation for JK flip flop is n+ =J n +K n n haracteristic Equation for flip flop is n+ = n T haracteristic Equation for T flip flop is n+ =T n +T n Page: 3

32 29. Explain the operation of a gated SR latch with a logic diagram and truth table. Logic diagram and truth table of gated SR flip flop is shown below: S S EN S R n+ n (No hange) EN R R x x Illegal n (No hange) Logic iagram Truth table When the Enable (EN) input is high, information at the R and S inputs will be transmitted directly to the outputs. The latch is said to be enabled. When the Enable (EN) input is low, the outputs of the AN gates are low and information at the R and S inputs will not be transmitted to the outputs. The latch is said to be disabled. It is possible to strobe or clock the flip flop in order to store information at any time and then hold the stored information for any desired period of time. This flip flop is called a gated or clocked RS flip flop. Page: 32

33 3. Explain the operation of edge triggered SR flip flop with the help of a logic diagram and truth table. Also draw the relevant waveforms. Answer: Positive edge triggered SR flip flop S S S PT R R R Logic iagram IEEE Symbol S R n+ n (No hange) ( Reset ) ( Set ) Illegal PT S R t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, S= and R=, hence no change in the output and =. At t, S= and R=, hence the output is set and =. At t 2, S= and R=, hence the output is reset and =. At t 3, S= and R=, hence the output is set and = At t 4, S= and R=, hence no change in the output and =. Waveform of positive edge triggered RS flip flop Page: 33

34 Negative edge triggered SR flip flop S S S NT R R R Logic iagram SR flip flop Symbol S R n+ n (No hange) ( Reset ) ( Set ) Illegal PT S R t t t 2 t 3 t 4 Truth table. Negative edges occur at t,t,t 2,t 3 and t 4. At t, S= and R=, hence no change in the output and =. At t, S= and R=, hence the output is set and =. At t 2, S= and R=, hence the output is reset and =. At t 3, S= and R=, hence the output is set and = At t 4, S= and R=, hence no change in the output and =. Waveform of negative edge triggered SR flip flop Page: 34

35 3. Explain the operation of edge triggered flip flop with the help of a logic diagram and truth table. Also draw the relevant waveforms. Answer: Positive edge triggered flip flop S PT R Logic iagram flip flop Symbol n+ x n (No hange) PT t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, =, hence the output is low and =. At t, =, hence the output is high and =. At t 2, =, hence the output is low and =. At t 3, =, hence the output is high and = At t 4, =, hence no change in the output and =. Waveform of positive edge triggered flip flop Page: 35

36 Negative triggered flip flop S NT R Logic iagram flip flop Symbol n+ x n (No hange) PT t t t 2 t 3 t 4 Truth table Negative edges occur at t,t,t 2,t 3 and t 4. At t, =, hence the output is low and =. At t, =, hence the output is high and =. At t 2, =, hence the output is low and =. At t 3, =, hence the output is high and = At t 4, =, hence no change in the output and =. Waveform of positive edge triggered flip flop Page: 36

37 32. Explain the working of pulse triggered JK flip flop with typical JK flip flop waveform. Answer: Positive Edge Triggered JK flip flop J S J PT K R K Logic iagram JK flip flop Symbol J K n+ n (No hange) Toggle PT J K t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, J= and K=, hence no change in the output and =. At t, J= and K=, hence the output is high and =. At t 2, J= and K=, hence the output is low and =. At t 3, J= and K=, hence the output is high and = At t 4, J= and K=, hence no change in the output and =. Waveform of positive edge triggered JK flip flop : Page: 37

38 Negative Edge Triggered JK flip flop J S J NT K R K Logic iagram JK flip flop Symbol J K n+ n (No hange) Toggle NT J K t t t 2 t 3 t 4 Truth table Waveform of positive edge triggered JK flip flop Negative edges occur at t,t,t 2,t 3 and t 4. At t, J= and K=, hence no change in the output and =. At t, J= and K=, hence the output is high and =. At t 2, J= and K=, hence the output is low and =. At t 3, J= and K=, hence the output is high and = At t 4, J= and K=, hence no change in the output and =. Page: 38

39 33. Explain the working of Master Slave J K flip flops with logic diagram. Answer: J J K K Master Slave flip flop Master is positive-level-triggered and the slave is negative-level-triggered. The master responds to its J and K inputs before the slave. If J= and K=, the master sets on the positive clock transition. The high output of the master drives the J input of the slave. So, on the negative clock transition, the slave sets, thus copying the action of the master. If J= and K=, the master resets on the positive clock transition. The high output of the master drives the K input of the slave. So, on the negative clock transition, the slave resets, thus copying the action of the master. If J= and K=, the master toggle on the positive clock transition. The slave also toggle at the negative clock transition thus copying the action of the master. If J= and K=, the master and the slave both are disabled, thus copying the action of the master. Page: 39

40 34. What is contact bounce? With neat diagram, explain the working principles of Switch e bounce circuit. Answer: 5V Voltage at A R 5V S A V Bounce Any mechanical switching device consists of a moving contact arm restrained by some spring system. As a result, when a mechanical switch is closed, the arm is moved from one stable position to other and the arm bounces much as a hard ball bounces when dropped on a hard surface. This phenomenon is known as contact bounce. When switch S is closed, due contact bounce the voltage at the A is shown in the above figure. RS Latch ebounce ircuit +V SW H R S L R 2 R When switch(sw) is moved to the position H, R= and S=. Bouncing occurs at S due to contact bounce of the switch. The flip flop treat as high and low inputs. The flip flop will be set with = at the firs high of the contact bounce. When the switch continue to bounce, losing contact, the input signals are R=S=, thus the flip flop remains at =. As a result, the flip flop responds only to the first high of the contact bounce. Page: 4

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