DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates.

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1 DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS AIM To design and implement encoders and decoders using logic gates. COMPONENTS REQUIRED S.No Components Specification Quantity 1. Digital IC Trainer Kit I/P AND Gate IC OR Gate IC NOT Gate IC AND Gate IC Connecting Wires - As required THEORY Encoder An Encoder is a digital circuit which has 2 n inputs and n output lines. In encoder the output lines generate the binary code corresponding to the input value. In octal to Binary encoder, it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder, it is assumed that only one input has a value of one at a given time otherwise the circuit is meaningless. It has an ambiguity that when all inputs are zero the outputs are zero. The zero outputs can also be generated when = 1. Decoder A decoder is a kind of combinational circuit that has multiple inputs and multiple output s, and used for conversion of coded inputs into the coded outputs. The bits in the input code are generally less than the bits that are present in the output code. A decoder basically decodes an input code. For example, if a binary code of n bits is provided to the decoder, then the decoder may tell that which code is this from the possible 2 n codes. PROCEDURE: Connections are given as per the circuit diagram. Logical inputs are given as per the truth table. Observe the outputs and verify the truth table. JJCET/EEE-LDIC LAB 4. 1

2 4:2 PRIORITY ENCODER A 4 to 2 priority encoder has four inputs,, & two outputs Y1 & Y0. Here, the input, has the highest priority, whereas the input, has the lowest priority. In this case, even if more than one input is 1 at the same time, the output will be the (binary) code corresponding to the input, which is having higher priority. We considered one more output, V in order to know, whether the code available at outputs is valid or not. If at least one input of the encoder is 1, then the code available at outputs is a valid one. In this case, the output, V will be equal to 1. If all the inputs of encoder are 0, then the code available at outputs is not a valid one. In this case, the output, V will be equal to 0. Block Diagram of 4:2 Priority Encoder Y0 Data 4:2 ENCODER Y1 Data Truth Table D 3 D 2 D 1 D 0 Y 1 Y 0 V X X X X X X Circuit Diagram JJCET/EEE-LDIC LAB 4. 2

3 8:3 PRIORITY ENCODER (OCTAL TO BINARY ENCODER) An octal to binary encoder consists of eight input lines and three output lines. Each input line corresponds to each octal digit and three outputs generate corresponding binary code. In encoders, it is to be assumed that only one input is active or has a value 1 at any given time otherwise the circuit has no meaning. From the truth table, the output Y2 becomes 1 if any of the digits D4 or D5 or D6 or D7 is one. Thus, we can write its expression as Y2 = D4 + D5 + D6 + D7 Similarly, Y1 = + + D6 + D7 Y0 = + + D5 + D7 Also it is to be observed that does not exist in any of the expressions so it is considered as don t care. From the above expressions, we can implement the octal to binary encoder using set of OR gates. Block Diagram of 8:3 Encoder B0 INPUTS D4 8:3 ENCODER B1 OUTPUT S D5 D6 B2 D7 JJCET/EEE-LDIC LAB 4. 3

4 Truth Table D4 D5 D6 D7 B0 B1 B Circuit Diagram JJCET/EEE-LDIC LAB 4. 4

5 2:4 BINARY DECODER In a 2-to-4 binary decoder, two inputs are decoded into four outputs hence it consists of two input lines and 4 output lines. Only one output is active at any time while the other outputs are maintained at logic 0 and the output which is held active or high is determined the two binary inputs A and B. Block Diagram of 2:4 Decoder A INPUTS 2:4 DECODER OUTPUTS B Truth Table A B D 0 D 1 D 2 D Circuit Diagram JJCET/EEE-LDIC LAB 4. 5

6 3:8 DECODER In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has three inputs as A, B, and C and eight output from through D7. Based on the combinations of the three inputs, only one of the eight outputs is selected. Block Diagram of 3:8 Decoder A INPUTS B 3:8 DECODER OUTPUTS D4 C D5 D6 D7 Truth Table A B C D4 D5 D6 D JJCET/EEE-LDIC LAB 4. 6

7 Circuit Diagram Result Thus the Encoders and Decoders were implemented using logic gates and their truth tables were verified. JJCET/EEE-LDIC LAB 4. 7