Combinational Logic. Jee-Hwan Ryu. School of Mechanical Engineering Korea University of Technology and Education

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1 MEC5 디지털공학 Combinational Logic Jee-Hwan Ryu School of Mechanical Engineering Combinational circuits Outputs are determined from the present inputs Consist of input/output variables and logic gates inary signal from registers inary signal to registers Sequential Circuits Outputs are determined from the present inputs and the state of the storage elements The state of the storage elements is a function of previous inputs Depends on present and past inputs

2 nalysis procedure To determine the function from a given circuit diagram nalysis procedure Make sure the circuit is combinational or sequential No Feedback and memory elements Obtain the output oolean functions or the truth table Obtain Procedure-oolean Function oolean function from a logic diagram Label all gate outputs with arbitrary symbols Make output functions at each level Substitute final outputs to input variables

3 Obtain Procedure-Truth Table Truth table from a logic diagram Put the input variables to binary numbers Determine the output value at each gate Obtain truth table Eample

4 Design Procedure Procedure to design a combinational circuit. Determine the required number of input and output from specification. ssign a symbol to each input/output. Derive the truth table from the required relationship 4. Obtain the simplified oolean functions 5. Draw the logic diagram and verify design correctness Code conversion eample CD to ecess- code converter Ecess- code : decimal digit+ Design procedure )Determine inputs/outputs Inputs :,,C,D ( ) Outputs : W,X,Y,Z ( )

5 Code conversion eample ) Derive truth table Code conversion eample ) Obtain simplified oolean functions

6 Code conversion eample 4) Draw the logic diagram Eample Design a combinational circuit with three inputs and one output. The output is when the binary value of the inputs is less than. The output is otherwise.

7 inary adder-subtractor inary adder Half adder : performs the addition of -bits (+y) Full adder : performs the addition of -bits (+y+z) Two half adder can be employed to a full adder Realization of inary adder-subtractor Half adder Full adder Cascade of n-full adder Providing a complementing circuit Half dder Sum of binary inputs Input : X(augend), Y(addend) Output : S(sum), C(carry) Sy + y Cy

8 Half dder Full adder Sum of binary inputs Input : X,Y( significant bits),z( carry bit) Output : S(sum),C(carry)

9 Full dder S z ( y) C z( y + y) z ( y + y) + z( y + y) y z + yz z ( y + y) + z( y + y ) y z + yz + yz + y z + y + y Full dder with Two Half dders and an OR

10 inary dder Sum of two n-bit binary numbers 4-bit adder, inary dder i P i i S i G i C i C i

11 inary Subtractor - equals +( complement of ) When M(act as adder) M(subtractor) Overflow Sum of n digit number occupies n+ digit lways occurs when two numbers are same sign (eamples of overflow)

12 Decimal dder Calculate binary and represent decimal in binary coded form 9 inputs and 5 outputs 4 bits for each decimal numbers input and output carry Wide variety of decimal adder circuit depending on the code In this Chapter, decimal adder for the CD code inary and CD Sum 9(addend)+9(augend)+(carry)9 (Maimum) CD Suminary Sum CD Sum inary Sum+

13 CD dder CD digit output of -CD digit sum Correction is needed K ~ CK + Z8Z4 + Z8Z inary Multiplier bit bit 4bit(ma)

14 (K-bit) (J-bit) (K J) ND gates, (J-) K-bit adder needed inary Multiplier ' ' ' ' ' ) ( ' ' ' ) ( ) ( < > Magnitude Comparator,,, ' ' + i for i i i i i only if the pair of bits in i are equal Compare from the most significant bit

15 Magnitude Comparator Decoders decoder is a combinational circuit that converts binary information from n input lines to a maimum of ^n unique output. Generate the ⁿ(or less) minterms of n input variables Eg) to 8 line decoder

16 -to-4-line Decoder With Enable Input Operates with complemented outputs complemented enable input Decoder With Enable InputDemultipleer Demultipleer circuit that receive information from a single line and directs it to one of ^n possible output lines -to-4-line decoder with enable input - to-4-line demultipleer E is taken as a data input line and are taken as the selection inputs

17 Decoders with enable inputs can be a larger decoder circuit 46 decoder by two 8 decoders w ~ w ~ Combinational Logic Implementation with Decoder ny combinational circuit can be implemented with line decoder and OR gates Eample) full adder S(, y, z) C(, y, z) (,,4,7) (,5,6,7)

18 Eample combinational circuit is defined by the following three oolean functions: F y z + z F y z + y F y z + y Design the circuit with a decoder and eternal gates. Encoders Inverse operation of a decoder Generate n outputs of ⁿ input values E) octal to binary encoder z D + D y D D 4 + D + D 5 + D 5 + D + D D 7 + D + D 7 7 Only one input can be active at any given time

19 Priority Encoder Problem happens two or more inputs equal to at the same time Give a priority function to circuit V is valid bit, when one or more inputs are, then inspect D D y D ( means, ) D V Eample Design a 4-input priority encoder with inputs as in Table 4-8, but with input D having the highest priority and input D the lowest priority

20 Multipleers Select a binary information from many input lines Directs it to a single output line Selection is controlled by a set of selection lines ⁿ input lines have n selection lines -to--line Multipleer I I Y I I MUX Y S S (a) Logic diagram (b) lock diagram

21 4-to--Line Multipleer Quadruple -to--line Multipleer

oolean Function Implementation with MUX MUX is essentially decoder includes OR gate Minterms of function are generated in a MUX n input variables First n- variables

22 oolean Function Implementation with MUX MUX is essentially decoder includes OR gate Minterms of function are generated in a MUX n input variables First n- variables -> input of MUX Remaining variable -> data inputs ( ) ( ),,6,7,, z y F oolean Function Implementation with MUX S S S MUX C D F C D F F D F D F D F F F D F F

23 Three-state Gates Three-state gates Logic, and high-impedance state High-impedance state behaves like an open circuit MUX with Three-state Gates Multipleers can be constructed with three-state gates

UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY

UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational