CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Multiplexers

Transcription

1 CSCI : Computer Architecture I Instructor: Pranava K. Jha Multiplexers Q. Develop a Boolean expression for the function F in terms of the input variables v, w, x, y and z in the following circuit. (E is the enable input.) of 6

2 All multiplexers are enabled, hence each will respond to the SELECT inputs and data inputs. Let g be the output of the top left multiplexer and let h be the output of the bottom left multiplexer, and note that g h = (w x ) + (w x) + (wx ) + (wx) = w x + wx, and = v (w x ) + v(w x) + (wx ) + (wx) = v w x + vw x + wx = v w x + (vw + w)x = v w x + (v + w)x, using absorption theorem, i.e., a+ a b = a + b = v w x + vx + wx. of 6

3 Accordingly, F = g(y z ) + (y z) + h(yz ) + (yz) = (w x + wx )y z + (v w x + vx + wx) yz + yz = (w x + wx )y z + [(v w x + vx + wx)z + z] y = (w x + wx )y z + [(v w x + vx + wx) + z] y, using absorption theorem = v w x y + vxy + wxy + w xy z + wx y z + yz. of 6

4 Q. The circuit below employs three -to- multiplexers, where E denotes the Enable input. Develop a Boolean expression for the function F in terms of the input variables v, w, x, y and z. I I I I E f S S v v I I I I w x f I I I I E S S f F E y z S S w x of 6

5 I I I I f w x + wx = x E S S v v I I I I E w x f vw x + w x + v wx = vw + w x + v wx I I I I E S S y z f F S S w x F = x y z + y z + (vw + w x + v wx )yz 5 of 6

6 Q. Realize the Boolean function f(w, x, y, z) = Σm(, 5, 7, 8,,, 5) using an 8-to- multiplexer and an inverter. Let inputs w, x and y appear on the SELECT lines. The canonical truth table and the abridged truth table appear below. Truth table w x y z f Abridged truth table w x y f z z z z z Implementation is immediate. 8-to- MUX w x y z S S S I I I I I I 5 I 6 I 7 Y f 6 of 6

7 Q. Consider the following Boolean function: f(a, B, C, D) = Σm (,,, 6, 9,,, ). Present an abridged truth table where inputs are deemed to be A, C and D. Truth table Abridged truth table A B C D f A C D f B B 7 of 6

8 Q. Realize the following Boolean function using -to- multiplexer and external gates: f(w, x, y, z) = Σm(, 5, 7, 8,,, 5). Let w and x appear on the SELECT lines. The truth table and the abridged truth table are immediate. Truth table w x y z f Abridged truth table w x f y + z z y z + yz Implementation follows. w x y z S S I I Y f I I 8 of 6

9 Q.. [ points] Present a truth table for the function f(w, x, y, z) = Σ(,, 6, 7, 8, 9, ), and then derive a condensed truth table where primary variables are y and z, and whose output is in terms of w, x, logical and logical. Truth table w x y z f Condensed truth table y z f w + x x w x w x 9 of 6

10 Q. Present the truth table of the function F relative to the input variables A, B, C and D in the following circuit. The following table is immediate. A B F D (C + D) CD Detailed truth table follows. A B C D F of 6

11 Q. IC 75 is a four-input, two-bit multiplexer. Its block diagram and function table appear below. Block diagram Function table G G A B G C C C C G C C C C 7x5 Y Y Inputs Outputs G G B A Y Y C C C C C C C C C C C C C C C C Show how to implement the Boolean function f(w, x, y) = Σm(,, 6, 7) using IC 75. You may use an external NOT gate and an external OR gate. The area of operation of the function table relevant to the present implementation is highlighted below. Inputs Outputs G G B A Y Y C C C C C C C C C C C C C C C C of 6

12 Implementation follows. of 6

13 Q. Show how to realize an 8-to- multiplexer using -to- multiplexers and -to- multiplexers. Recall the block diagrams of -to- MUX, and 8-to- MUX. I I -to- MUX f = S I + SI S J J J 7 g = S S J + S S J + S S J + S S J J 5 6 S S K 8-to- MUX K K K K K 5 K h = T T T K + T T T K + T T T K + T T T K + T T T K + T T T K 5 + T T T K 6 + T T T K 7 K T T T Note: Pin numbers have been assigned for ease of implementation. of 6

14 It is clear that h = T (T T K + T T K + T T K + T T K ) + T (T T K + T T K 5 + T T K 6 + T T K 7 ). A desired implementation is now immediate. K K T T K + T T K + T T K + T T K K K K -to- MUX h K 5 K 6 K 7 7 T T K + T T K 5 + T T K 6 + T T K T T T Remark: The following tree structure is an abstraction of the preceding implementation. -to- MUX of 6

15 There exists another way of realizing an 8-to- MUX. To that end, note that h = T T (T K + T K ) + T T (T K + T K ) + T T (T K + T K 5) + T T (T K 6 + T K 7 ). -to- MUX T K + T K K K K K K K 5 K 6 K 7 -to- MUX -to- MUX T K + T K T K + T K h -to- MUX T K 6 + T K 7 T T T The tree structure follows. -to- MUX -to- MUX -to- MUX -to- MUX 5 of 6

16 An 8-to- MUX may as well be implemented by employing -to- MUXs uniformly. Here is he underlying tree structure. -to- MUX -to- MUX -to- MUX -to- MUX -to- MUX -to- MUX -to- MUX The foregoing discussion on tree structures underlying the construction of a large multiplexer using smaller ones admits an elegant generalization. Let n, i and j be positive integers such that n = i + j, so n i j =. A n -to- MUX is realizable by means of i -to- MUX ( j nos.) and j -to- MUX ( no.). The schematic follows. i -to- MUX j - i -to- MUX i -to- MUX j -to- MUX Note that if i, then a i -to- MUX itself is obtainable by means of smaller multiplexers using the same scheme. The tree corresponding to the implementation of a n -to- multiplexer using -to- multiplexers is a complete binary tree having n nodes. o 6 of 6