CprE 281: Digital Logic
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1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 Code Converters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 HW 7 is out Administrative Stuff It is due next Monday (Oct 4pm
4 Administrative Stuff The second midterm is in 2 weeks.
5 Midterm Exam #2 Administrative Stuff When: Friday October 4pm. Where: This classroom What: Chapters, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten/typed notes).
6 Midterm 2: Format The exam will be out of 3 points You need 95 points to get an A on the exam It will be great if you can score more than points. but you can t roll over your extra points L
7 Quick Review
8 Decoders
9 2-to-4 Decoder (Definition) Has two inputs: w and w Has four outputs: y, y, y 2, and y 3 If w = and w =, then the output y is set to If w = and w =, then the output y is set to If w = and w =, then the output y 2 is set to If w = and w =, then the output y 3 is set to Only one output is set to. All others are set to.
10 Truth Table and Graphical Symbol for a 2-to-4 Decoder [ Figure 4.3a-b from the textbook ]
11 Truth Table and Graphical Symbol for a 2-to-4 Decoder The outputs are one-hot encoded [ Figure 4.3a-b from the textbook ]
12 Truth Logic Circuit for a 2-to-4 Decoder [ Figure 4.3c from the textbook ]
13 Adding an Enable Input En [ Figure 4.3c from the textbook ]
14 Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.4a-b from the textbook ]
15 Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input x indicates that it does not matter what the value of these variable is for this row of the truth table [ Figure 4.4a-b from the textbook ]
16 Graphical Symbol for a Binary n-to-2 n Decoder with an Enable Input A binary decoder with n inputs has 2 n outputs The outputs of an enabled binary decoder are one-hot encoded, meaning that only a single bit is set to, i.e., it is hot. [ Figure 4.4d from the textbook ]
17 A 3-to-8 decoder using two 2-to-4 decoders w y w y w w 2 w y y 2 En y 3 y y 2 y 3 En w y y 4 w y y 2 En y 3 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
18 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
19 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
20 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
21 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
22 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
23 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
24 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
25 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
26 A 3-to-8 decoder using two 2-to-4 decoders w w y y w w y y y 2 y 2 w 2 En y 3 y 3 En w En y w y y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
27 A 4-to-6 decoder built using a decoder tree w w y y w w En y y 2 y 3 y y 2 y 3 w 2 w 3 En w y w y y 2 En y 3 w w y y 2 En y 3 w y y w w y y 2 En y 3 y 4 y 5 y 6 y 7 y 8 y 9 y y [ Figure 4.6 from the textbook ] w y w y y 2 En y 3 y 2 y 3 y 4 y 5
28 Let s build a 5-to-32 decoder
29 Let s build a 5-to-32 decoder y y 5 En y 6 y 3
30 Let s build a 5-to-32 decoder w w w 2 w 3 y y 5 w 4 En w w w 2 w 3 y 6 y 3
31 Demultiplexers
32 -to-4 Demultiplexer (Definition) Has one data input line: D Has two output select lines: w and w Has four outputs: y, y, y 2, and y 3 If w = and w =, then the output y is set to D If w = and w =, then the output y is set to D If w = and w =, then the output y 2 is set to D If w = and w =, then the output y 3 is set to D Only one output is set to D. All others are set to.
33 A -to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.4c from the textbook ]
34 A -to-4 demultiplexer built with a 2-to-4 decoder output select lines the four output lines data input line D [ Figure 4.4c from the textbook ]
35 Multiplexers (Implemented with Decoders)
36 A 4-to- multiplexer built using a 2-to-4 decoder w w s s w y w y y 2 w 2 En y 3 f w 3 [ Figure 4.7 from the textbook ]
37 Encoders
38 Binary Encoders
39 4-to-2 Binary Encoder (Definition) Has four inputs: w 3, w 2, w, and w Has two outputs: y and y Only one input is set to ( one-hot encoded). All others are set to. If w = then y = and y = If w = then y = and y = If w 2 = then y = and y = If w 3 = then y = and y =
40 Truth table for a 4-to-2 binary encoder w 3 w 2 w w y y [ Figure 4.9 from the textbook ]
41 Truth table for a 4-to-2 binary encoder w 3 w 2 w w y y The inputs are one-hot encoded [ Figure 4.9 from the textbook ]
42 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w w y w 2 w 3 y [ Figure 4.9 from the textbook ]
43 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w? w y w 2 w 3 y [ Figure 4.9 from the textbook ]
44 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w It is assumed that the inputs are one hot encoded w y w 2 w 3 y [ Figure 4.9 from the textbook ]
45 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w w w 2 y w 3 y [ Figure 4.9 from the textbook ]
46 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w w w 2 y w 3 y [ Figure 4.9 from the textbook ]
47 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w w w 2 y w 3 y [ Figure 4.9 from the textbook ]
48 Circuit for a 4-to-2 binary encoder w 3 w 2 w w y y w w w 2 y w 3 y [ Figure 4.9 from the textbook ]
49 A 2 n -to-n binary encoder 2 n inputs w w 2 n y y n n outputs [ Figure 4.8 from the textbook ]
50 Priority Encoders
51 Truth table for a 4-to-2 priority encoder (abbreviated version) w 3 w 2 w w y y z x x x x x x d d [ Figure 4.2 from the textbook ]
52 Truth table for a 4-to-2 priority encoder (abbreviated version) w 3 w 2 w w y y z x x x x x x d d [ Figure 4.2 from the textbook ]
53 Truth table for a 4-to-2 priority encoder x x x x x x w 3 w 2 w w y y z d d
54 Expressions for 4-to-2 priority encoder w 3 w 2 w w y y z d d w 3 w 2 w w d y = w 3 + w 2
55 Expressions for 4-to-2 priority encoder w 3 w 2 w w y y z d d w 3 w 2 w w d y = w 3 + w w 2
56 Expressions for 4-to-2 priority encoder w 3 w 2 w w y y z d d w 3 w 2 w w z = w 3 + w 2 + w + w
57 Circuit for the 4-to-2 priority encoder w 3 w 2 w w y y z
58 d w y d y z x x x w x x w 2 x w 3 The textbook derives a different circuit for the 4-to-2 priority encoder using a 4-to-2 binary encoder
59 The textbook derives a different circuit for the 4-to-2 priority encoder using a 4-to-2 binary encoder w 3 w 2 w w y y z x x x x x x d d w w y w 2 w 3 y
60 The textbook derives a different circuit for the 4-to-2 priority encoder using a 4-to-2 binary encoder w 3 w 2 w w y y z x x x x x x d d i w i w y i 2 w 2 i 3 w 3 y i + i + i 2 + i 3 z
61 The textbook derives a different circuit for the 4-to-2 priority encoder using a 4-to-2 binary encoder w 3 w 2 w w y y z x x x x x x d d i w i w y i 2 w 2 i 3 w 3 y i + i + i 2 + i 3 z Try to prove that this is equivalent to the circuit that was derived above.
62 Code Converters
63 Code Converter (Definition) Converts from one type of input encoding to a different type of output encoding.
64 Code Converter (Definition) Converts from one type of input encoding to a different type of output encoding. A decoder does that as well, but its outputs are always one-hot encoded so the output code is really only one type of output code. A binary encoder does that as well but its inputs are always one-hot encoded so the input code is really only one type of input code.
65 A hex-to-7-segment display code converter [ Figure 4.2 from the textbook ]
66 A hex-to-7-segment display code converter [ Figure 4.2 from the textbook ]
67 A hex-to-7-segment display code converter [ Figure 4.2 from the textbook ]
68 A hex-to-7-segment display code converter [ Figure 4.2 from the textbook ]
69 A hex-to-7-segment display code converter [ Figure 4.2 from the textbook ]
70 What is the circuit for this code converter? x 3 x 2 x x
71 What is the circuit for this code converter? x 3 x 2 x x f(x, x 2, x 3, x 4 ) = Σ m(, 2, 3, 5, 6, 7, 8, 9,, 2, 4, 5)
72 What is the circuit for this code converter? x 3 x 2 x x x x x 2 x 3 x 4 m m 4 m 2 m 8 x 3 m m 5 m 3 m 2 m 6 m 3 m 7 m 5 m 4 m 9 m m x 4 x 2 f(x, x 2, x 3, x 4 ) = Σ m(, 2, 3, 5, 6, 7, 8, 9,, 2, 4, 5)
73 What is the circuit for this code converter? x 3 x 2 x x
74 What is the circuit for this code converter? x 3 x 2 x x x x x 2 x 3 x 4 m m 4 m 2 m 8 x 3 m m 5 m 3 m 2 m 6 m 3 m 7 m 5 m 4 m 9 m m x 4 x 2 f(x, x 2, x 3, x 4 ) = Σ m(, 2, 3, 5, 6, 8, 9,, 2, 3, 4)
75 Arithmetic Comparison Circuits
76 Truth table for a one-bit digital comparator [
77 A one-bit digital comparator circuit [
78 Truth table for a two-bit digital comparator [
79 A two-bit digital comparator circuit [
80 A four-bit comparator circuit [ Figure 4.22 from the textbook ]
81 Example Problems from Chapter 4
82 Example : SOP vs Decoders Implement the function f(w, w 2, w 3 ) = Σ m(,, 3, 4, 6, 7) by using a 3-to-8 binary decoder and one OR gate.
83 Solution Circuit w 3 w y w 2 w w w 2 y y 2 y 3 y 4 y 5 y 6 En y 7 f(w, w 2, w 3 ) = Σ m(,, 3, 4, 6, 7) [ Figure 4.44 from the textbook ]
84 Notice this swap of variables in the two lists. w 3 w Solution Circuit y w 2 w w w 2 Need to match the least significant with the least significant in both. y y 2 y 3 y 4 y 5 y 6 En y 7 f(w, w 2, w 3 ) = Σ m(,, 3, 4, 6, 7) [ Figure 4.44 from the textbook ]
85 Example 2: Implement an 8-to-3 binary encoder [ Figure 4.45 from the textbook ]
86 Example 2: Implement an 8-to-3 binary encoder y = w + w 3 + w 5 + w 7 y = w 2 + w 3 + w 6 + w 7 y 2 = w 4 + w 5 + w 6 + w 7 [ Figure 4.45 from the textbook ]
87 Circuit for the 8-to-3 binary encoder w 7 w 6 w 5 w 4 w 3 w 2 w w y y y 2 y = w + w 3 + w 5 + w 7 y = w 2 + w 3 + w 6 + w 7 y 2 = w 4 + w 5 + w 6 + w 7
88 Example 3: Implement an 8-to-3 priority encoder
89 Example 3: Implement an 8-to-3 priority encoder x x x x x x x x x x x x x x x x x x x x x x x x x x x x
90 Example 3: Implement an 8-to-3 priority encoder x x x x x x x x x x x x x x x x x x x x x x x x x x x x d d d z
91 Example 3: Implement an 8-to-3 priority encoder x x x x x x x x x x x x x x x x x x x x x x x x x x x x d d d z
92 Example 3: Implement an 8-to-3 priority encoder i = w 7 w 6 w 5 w 4 w 3 w 2 w w i = w 7 w 6 w 5 w 4 w 3 w 2 w i 2 = w 7 w 6 w 5 w 4 w 3 w 2 i 3 = w 7 w 6 w 5 w 4 w 3 i 4 = w 7 w 6 w 5 w 4 i 5 = w 7 w 6 w 5 i 6 = w 7 w 6 i 7 = w 7 z = i +i +i 2 +i 3 +i 4 +i 5 +i 6 +i 7 x x x x x x x x x x x x x x x x x x x x x x x x x x x x d d d z
93 Circuit for the 8-to-3 binary encoder w 7 w 6 w 5 w 4 w 3 w 2 w w y y y 2
94 Circuit for the 8-to-3 priority encoder i 7 i 6 i 5 i 4 i 3 i 2 i i w 7 w 6 w 5 w 4 w 3 w 2 w w y y y 2 z
95 Example 4:Circuit implementation using a multiplexer Implement the function f(w, w 2, w 3, w 4, w 5 ) = w w 2 w 4 w 5 + w w 2 + w w 3 + w w 4 + w 3 w 4 w 5 using a 4-to- multiplexer
96 Some Boolean Algebra Leads To w w 2 w 4 w 5 + w w 2 + w w 3 + w w 4 + w 3 w 4 w 5 w w 4 (w 5 w 2 ) + w 4 (w 3 w 5 ) + w (w 2 + w 3 ) + w w 4 () w w 4 (w 5 w 2 ) + ( w +w )w 4 (w 3 w 5 ) + w ( w 4 +w 4 ) (w 2 + w 3 ) + w w 4 () w w 4 (w 5 w 2 ) + w w 4 (w 3 w 5 ) + w w 4 (w 2 + w 3 ) + w w 4 ( w 3 w 5 + (w 2 +w 3 ) + ) w w 4 (w 5 w 2 ) + w w 4 (w 3 w 5 ) + w w 4 (w 2 + w 3 ) + w w 4 () Note that the split is by w and w 4, not w and w 2
97 Solution Circuit [ Figure 4.46 from the textbook ]
98 Some Final Things from Chapter 4
99 A shifter circuit [ Figure 4.5 from the textbook ]
100 A shifter circuit
101 A shifter circuit
102 A shifter circuit w 3 w 2 w w No shift in this case.
103 A shifter circuit
104 A shifter circuit
105 A shifter circuit w 3 w 2 w Shift to the right by bit
106 A shifter circuit w 3 w 2 w w Shift to the right by bit
107 A barrel shifter circuit [ Figure 4.5 from the textbook ]
108 Questions?
109 THE END
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