CHAPTER * 2-2.* Pearson Education Limited Problem Solutions, Global Edition Chapter 2. Verification of DeMorgan s Theorem

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1 HPTER 2 2-.* a) XYZ = X + Y + Z Verification of DeMorgan s Theorem Pearson Education Limited 206. X Y Z XYZ XYZ X + Y + Z b) X + YZ = ( X + Y) ( X + Z) The Second Distributive Law X Y Z YZ X + YZ X + Y X + Z (X + Y)(X + Z) c) XY + YZ + XZ = XY + YZ + XZ X Y Z XY YZ XZ XY + YZ + XZ XY YZ XZ XY + YZ + XZ * a) X Y + XY + XY = X + Y = ( X Y + X Y ) + ( XY + XY ) = XY ( + Y) + YX ( + X) = X + Y

2 b) = = ( + ) + ( + ) = ( + ) + ( + ) + = c) Y + XZ + XY = X + Y + Z = Y + XY + XZ = ( Y + X )( Y + Y ) + XZ = Y + X + XZ = Y + ( X + X)( X + Z) = X + Y + Z d) XY + Y Z + XZ + XY + YZ = X Y + XZ + YZ = XY + YZ ( X + X ) + XZ + XY + YZ = XY + XYZ + XYZ + XZ + XY + YZ = XY ( + Z) + XYZ + XZ + XY + YZ = XY + XZ( + Y ) + XY + YZ = XY + XZ + XY ( Z + Z ) + YZ = XY + XZ + XYZ + YZ ( + X ) = XY + XZ( + Y ) + YZ = XY + XZ + YZ a) + D + + D = + D = D + D + D = ( + ) + ( D + D) + + D = D = + + D = + D b) WY + WYZ + WXZ + WXY = WY + WXZ + XYZ + XYZ = ( WY + WXYZ ) + ( WXYZ + WXYZ ) + ( WXYZ + WXYZ ) + ( WXYZ + WXY Z ) = ( WY + WXYZ ) + ( WXYZ + WXY Z ) + ( WXYZ + WXYZ ) + ( WXYZ + WXYZ ) = WY + WXZ ( Y + Y ) + XYZ ( W + W ) + XYZ ( W + W ) = WY + WXZ + XYZ + XYZ c) D + + D + = ( D)( D) = D + + D + = ( + D)( + )( + D)( + ) = ( + D + D)( + D + D) = D + D = ( D)( D) = ( D)( D) 2

3 Given: = 0, + = Prove: ( + )( + )( + ) = = ( + + )( + ) = + + = 0 + ( + ) = ( + )(0) = ( + )( + ) = ( + + ) = Step : Define all elements of the algebra as four bit vectors such as, and : Step 2: = ( 3, 2,, 0 ) = ( 3, 2,, 0 ) = ( 3, 2,, 0 ) Define OR, ND and NOT so that they conform to the definitions of ND, OR and NOT presented in Table 2-. a) + = is defined such that for all i, i = 0,...,3, i equals the OR of i and i. b) = is defined such that for all i, i = 0,...,3, i equals the ND of i and i. c) The element 0 is defined such that for = 0, for all i, i = 0,...,3, i equals logical 0. d) The element is defined such that for =, for all i, i = 0,...,3, i equals logical. e) For any element, is defined such that for all i, i = 0,...,3, i equals the NOT of i a) WXY + WY + XYW + WXY = XY + WY + WXY = XY ( + W ) + WY = XY + WY b) ( W + X)( W + Y + X ) ( W + X)( W + Y) + X( W + X) = WY + WX + XY + XW c) XYZ + XYZ + XYZ + XZ = XY + XZ + XYZ = XY + XZ d) ( W + X + Y)( X + Y) = WXY( X + Y) = WXY e) WXY + XYZ + XY + YZ + WXY = WXY + XYZ + XY + YZ = WXY + X ( Y + Z ) + YZ = XW + XY + XZ + YZ 2-7.* a) XY + XYZ + XY = X + XYZ = ( X + XY)( X + Z) = ( X + X )( X + Y)( X + Z) = ( X + Y)( X + Z) = X + YZ 3

4 b) X + Y( Z+ X + Z) = X + Y( Z+ XZ) = X + Y( Z+ X)( Z+ Z) = X + YZ+ XY = ( X + X)( X + Y) + YZ = X + Y+ YZ = X + Y c) WX ( Z + YZ ) + X ( W + WYZ ) = WXZ + WXYZ + WX + WXYZ = WXZ + WXZ + WX = WX + WX = X d) ( + )( D + D ) + = D + D + D + D + + = D + + = + + ( D ) = + + ( D) = + + D 2-8. a) XY + WY + WX = Y ( X + W ) + WX = Y + X + W + W + X b) XY + WY + WX = XY. WY. WX c) Y ( X + W ) + WX = YWX 2-9.* a) F = ( + )( + ) b) F= (( V+ WX ) + YZ ) c) F = [ W + X + ( Y + Z )( Y + Z)][ W + X + YZ + YZ ] d) F = + ( + ) + ( + ) 2-0.* Truth Tables a, b, c X Y Z a b W X Y Z c

5 a) Sum of Minterms: XYZ + XYZ + XYZ + XYZ Product of Maxterms: ( X + Y+ Z)( X + Y+ Z)( X + Y + Z)( X + Y+ Z) b) Sum of Minterms: Product of Maxterms: ( + + )( + + )( + + )( + + ) c) Sum of Minterms: WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ Product of Maxterms: ( W+ X + Y+ Z)( W+ X + Y+ Z)( W+ X + Y + Z) ( W+ X + Y+ Z)( W+ X + Y+ Z)( W+ X + Y + Z) ( W+ X + Y+ Z)( W+ X + Y+ Z)( W+ X + Y + Z) * a) F =Σ m(3, 4, 5, 6, 7) =ΠM (0,, 2) E =Σ m(, 3, 6, 7) =ΠM (0, 2, 4, 5) b) F = ΠM (3, 4, 5, 6, 7) E = ΠM (, 3, 6, 7) c) F + E =Σm (, 3, 4, 5, 6, 7) F E =Σm (3, 6, 7) d) F + E = XYZ + XYZ + XY Z + XYZ + XYZ + XYZ F E = XYZ + XYZ + XYZ e) XYZ + XYZ + XYZ = XYZ + XY = YX + ZY a) ( + )( + D ) = + D + = + s.o.p. = ( + ) p.o.s. b) X + X( X + Y)( Y+ Z) = ( X + X)( X + ( X + Y)( Y+ Z)) = ( X + X + Y)( X + Y+ Z) p.o.s. = ( + Y)( X + Y+ Z) = X + Y+ Z s.o.p. c) ( + + D )( + EF ) = ( + + )( + + D)( + + D)( + EF ) = ( + + )( + + D)( + + D)( + E)( + F) p.o.s. ( + + D )( + EF ) = ( + EF ) + ( + EF ) + D( + EF ) = + EF + EF + D + DEF s.o.p Y Z Y Z X W Y D a) b) c) X Z D 5

6 2-4. a) b) c) d) * a) Y b) c) X Z XZ + XY a) b) c) d) D D + + D + D + D + a) b) D + D * a) b) Y c) Y X X W Z Z D Σ m(3, 5, 6, 7) Σ m(3, 4, 5, 7, 9, 3, 4, 5) Σ m(0, 2, 6, 7, 8, 0, 3, 5) 6

7 2-9.* a) Prime = XZ, WX, XZ, WZ b) Prime = D,, D, D, c) Prime =,, D,, D, D Essential = XZ, XZ Essential =, D, D Essential =,, D a) b) c) Prime = D Prime = D, D Prime = D, D Essential = D,, Essential = D, D Essential = D, D, D F = D + D F = D + D F = D + D + D 2-2. a) b) ( + D)( + ) ( + D)( + ) 2-22.* a) s.o.p. D + + D b) s.o.p. + D + D c) s.o.p. D + D + ( or D) p.o.s. ( + D)( + D)( + + ) p.o.s. ( + D)( + D)( + + ) p.o.s. ( + )( + D)( + + D) a) b) POS = ( + + D)( + D)( + ) SOP = D + D + + D POS = ( + + D)( + + D) SOP = + + D 7

8 2-24. a) b) c) ?? 00 00?? 0 0 0???? 0 0?? * + + D + D + D + a) b) Y c) X X X X X X X X W X X X X Z D Primes =,,, Primes = XZ, XZ, WXY, WXY, WYZ, WYZ Primes =,, D, D Essential =,, Essential = XZ Essential =, D F = + + F = XZ + WXY + WXY F = + D( D or ) a) b) ? 0? 0??? 0?? 0? POS = ( + + )( + D)( + ) SOP = D + + POS = ( + + D)( + D)( + D) SOP = D + D + D 2-27.* X Y = XY + XY Dual(X Y) = Dual( XY + XY) = ( X + Y)( X + Y) = XY + XY = XY + XY = X Y 8

9 2-28. D + D + D = D + ( D) Note that X + Y = ( X Y) + XY Letting X = D and Y = D, We can observe from the map below or determine algebraically that XY is equal to 0. D For this situation, X + Y = ( X Y) + XY = ( X Y) + 0 = X Y So, we can write F(,,, D) = X Y = D ( D) D F 2-29.* The longest path is from input or D ns ns ns ns = ns a) b) c) ns 9

10 2-3. a) t PHL-, D to F = 2t PLH + 2 t PHL = 2(0.36) + 2(0.20) =.2 ns t PLH-, D to F = 2t PHL + 2t PLH = 2(0.20) + 2(0.36) =.2 ns t pd =.2 ns t = 2t PHL + t PLH = 2(0.20) + (0.36) = 0.76 ns PHL- to F t = 2t PHL + t PLH = 2(0.36) + (0.20) = ns PLH- to F t = = 0.84 ns pd- to F t = t PLH + t PHL = = 0.56 ns PHL-,, to F t = t PHL + t PLH = = 0.56 ns PLH-,, to F t = 0.56 ns pd-,, to F b) t = 4 t = 4(0.28) =.2 ns pd-, D to F pd t = 3 t = 3(0.28) = 0.78 ns pd- to F pd t to F = 2 t = 2(0.28) = 0.56 ns pd-,, pd c) For paths through an odd number of inverting gates with unequal gate t PHL and t PLH, path t PHL, t PLH, and t pd are different. For paths through an even number of inverting gates, path t PHL, t PLH, and t pd are equal If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before it can be predicted whether or not it is to occur due to the rejection time. For example, with a delay of 2 ns and a rejection time of 3 ns, for a 2.5 ns pulse, the initial edge will have already appeared at the output before the 3 ns has elapsed at which whether to reject or not is to be determined a) The propagation delay is t = max( t = 0.05, t = 0.0) = 0.0 ns. pd PHL PLH ssuming that the gate is an inverter, for a positive output pulse, the following actually occurs: 0.0 ns 0.05 ns If the input pulse is narrower than 0.05 ns, no output pulse occurs so the rejection time is 0.05 ns. The resulting model predicts the following results, which differ from the actual delay behavior, but models the rejection behavior: : 0.0 ns 0.0 ns b) For a negative output pulse, the following actually occurs: 0.5ns 0.05ns 0.0ns The model predicts the following results, which differs from the actual delay behavior and from the actual rejection behavior: 0

11 0.0ns 0.0ns Overall, the model is inaccurate for both cases a and b, and provides a faulty rejection model for case b. Using an average of t PHL and t PLH for t pd would improve the delay accuracy of the model for circuit applications, but the rejection model still fails * X N N 2 X 2 X 3 X 4 N 3 N 5 N 4 N 6 f Figure 4-40: Structural VHDL Description library ieee; use ieee.std_logic_64.all; entity nand2 is port(in, in2: in std_logic; out : out std_logic); end nand2; architecture concurrent of nand2 is begin out <= not (in and in2); end architecture; library ieee; use ieee.std_logic_64.all; entity nand3 is port(in, in2, in3 : in std_logic; out : out std_logic); end nand3; architecture concurrent of nand3 is begin out <= not (in and in2 and in3); end concurrent; library ieee; use ieee.std_logic_64.all; entity nand4 is port(in, in2, in3, in4: in std_logic; out : out std_logic); end nand4; -- The code above this point could be eliminated by using the library, func_prims. library ieee; use ieee.std_logic_64.all; entity fig440 is port(x: in std_logic_vector(2 to 0); f: out std_logic);

12 end fig440; architecture structural_2 of fig440 is component NND2 port(in, in2: in std_logic; out: out std_logic); end component; component NND3 port(in, in2, in3: in std_logic; out: out std_logic); end component; signal T: std_logic_vector(0 to 4); begin g0: NND2 port map (X(2),X(),T(0)); g: NND2 port map (X(2),T(0),T()); g2: NND2 port map (X(),T(0),T(2)); g3: NND3 port map (X(),T(),T(2),T(3)); g4: NND2 port map (X(),T(2),T(4)); g5: NND2 port map (T(3),T(4),f); end structural_2; F= XX XX begin g0: NOT_ port map (D, x); X = D + g: ND_2 port map (,, x2); Y = D g2: NOR_2 port map (, x, x3); g3: NND_2 port map (x, x3, x4); g4: OR_2 port map (x, x2, x5); g5: ND_2 port map (x4, x5, X); g6: ND_2 port map (x3, x5, Y); end structural_; 2

13 2-37. a b a c b c b a c d f g 2-38.* begin F <= (X and Z) or ((not Y) and Z); end; 2-39.* X N N 2 X 2 X 3 X 4 N 3 N 5 N 4 N 6 f module circuit_4_50(,,, D, X, Y); input,,, D; output X, Y; wire n, n2, n3, n4, n5; not go(n, D); nand g(n4, n, n3); and g2(n2,, ), g3(x, n4, n5), g4(y, n3, n5); or g5(n5, n, n2); nor g6(n3, n, ); endmodule 3

14 2-4. module circuit_4_5(x, F); input [2:0] X; output F; wire [0:4] T; nand g0(t[0],x[0],x[]), g(t[],x[0],t[0]), g2(t[2],x[],t[0]), g3(t[3],x[2],t[],t[2]), g4(t[4],x[2],t[2]), g5(f,t[3],t[4]); endmodule a b a c b c b a c d f g 2-43.* module circuit_4_53(x, Y, Z, F); input X, Y, Z; output F; assign F = (X & Z) (Z & ~Y); endmodule 4

CHAPTER * 6-2. a) 3-input NAND gate b) 4-input NOR gate * Pearson Education, Inc. a) F = (A + B) C D. b) G = (A + B) (C + D)

CHAPTER * 6-2. a) 3-input NAND gate b) 4-input NOR gate * Pearson Education, Inc. a) F = (A + B) C D. b) G = (A + B) (C + D) HPTER 6 6-.* a) = ( + ) b) G = ( + ) ( + ) 200 Pearson Education, Inc. 6-2. a) 3-input NN gate b) 4-input NOR gate +V +V 6-3. 6 inputs 6 inputs 6 inputs 6-4.* The longest path is from input or. 0.073 ns