Section:3 ISE A & BMax Marks: 50 Subject & code: Logic Design (10CS33) Name of faculty:mrs Deepti C Date: SOLUTIONS

Size: px

Start display at page:

Download "Section:3 ISE A & BMax Marks: 50 Subject & code: Logic Design (10CS33) Name of faculty:mrs Deepti C Date: SOLUTIONS"

Marilyn Dickerson
6 years ago
Views:

1 Third Semester B.E. IA Test-I, 2015 USN 1 P E I S PESIT Bangalore South Campus (Hosur Road, 1KM before Electronic City, Bangalore ) Department of Information Science &Engineering Section:3 ISE A & BMax Marks: 50 Subject & code: Logic Design (10CS33) Time: 90 Minutes. Name of faculty:mrs Deepti C Date: SOLUTIONS 1a.Write the truth table of the logic circuit having 3 inputs A, B and C. The output is expressed as y = AB C + ABC. Also simplify the expression using Boolean algebra. (05 Marks) A B C Y Simplified Expression=AC 1b.Define rise time, fall time in a digital waveform. What is the value of high duty cycle if the frequency of a digital waveform is 5 MHz and the width of the positive pulse is 0.05 µs?(05 Marks) Rise Time-The time required for Vo to make the transition from its low level to its high level is defined as rise time tr.it is measured between 1.1 L and 0.9 H. Fall Time-The time required for Vo to make the transition from its high level to its low level is defined as fall time tf. For ease of measurement we use 0.9 H and 1.1 L. T=1/f=1/5 MHz=0.2µs Duty cycle H = th / T =0.05/0.2=0.25 or 25%

2 2.a) Write a Verilog HDL code using structural model for two input AND gate and prepare test bench to simulate the circuit. Draw the timing diagram generated by simulating the Verilog code. Assume 20 ns holding time of each input combination. (06 Marks) modulebuild_and (y, a, b); input a, b; output y; and a1 (y, a, b); endmodule moduleandgate_two; input a, b; output y; andgatemy_gate(y,a,b); initial begin $monitor(y,a,b); a = 1'b0; b = 1'b0; #20 a = 1'b0; b = 1'b1; #20 a = 1'b1; b = 1'b0; #20 a = 1'b1; b = 1'b1; end endmodule 2b. What are Universal gates? Implement the basic gates using NAND gates only (04 Marks) A universal gate is a gate which can implement any Boolean function without need to use anyother gate type. The NAND and NOR gates are universal gates. Implementing an Inverter Using only NAND Gate Implementing AND Using only NAND Gates Implementing OR Using only NAND Gates Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOTfunctions.

3 3. a)draw the truth table and explain how a TTL 2 input NAND gateworks(6 Marks) The circuit consists of multiple-emitter input transistor Q1, phase-splitter transistor Q2, and totem-poletransistors Q3 and Q4. When all inputs are HIGH (> 2 volts) the current in R1 flows through the collector of Q1 into the base of Q2, turning on Q2. This turns on Q4 and turns off Q3, and the output voltage is LOW.If any input goes LOW (< 0.8 volts), the current in R1 flows through emitter of Q1, out of the input lead into ground. Q2 is turned off, turning off Q4 and turning on Q3, resulting in a HIGH output voltage. Except during the transitions, transistors Q1, Q2 and Q4 are always either saturated or cut off. The output structure consisting of Q3 and Q4 is called totem pole.

4 3b)Discuss positive and negative logic and list equivalences in positive and negative logic(4 Marks) The table below shows the two assignments that define positive and negative logic systems. Positive Logic Negative Logic H = 1 H = 0 L = 0 L = 1 The logical interpretation of a gate depends on whether positive or negative logic is assumed. In positive logic Low voltage (ex. 0 V) Logic 0 High voltage (ex. + 5 V) Logic 1 In negative logic High voltage (ex. 0 V) Logic 0 Low voltage (ex. - 5 V) Logic 1 For example: Gate Behavior X Y F X Y Positive Logic AN D Negative Logic X Y OR L L L L H L Gate Behavior Positive Logic Negative Logic X Y F X Y XOR X Y XNOR L L L L H H H L H H H L H L L H H H Equivalences:

5 4. a) A system has four inputs. The output will be high only when majority of the inputs are high. Find the following i)give the truth table and simplify by using K-Map ii)boolean expression in m and πm form iii)implement the simplified equation using NAND - NAND gates (5 Marks) A B C D Y cd ab Y= m(7,11,13,14,15)=πm(1,2,3,4,5,6,8,9,10,12)=abd+abc+bcd+acd 4b) Draw Karnaugh map of Y = F (A, B, C, D) =πm (0, 1, 2, 4, 5, 10).d (8, 9, 11, 12, 13, 15) and get the simplified POS form of K-Map. (5 Marks) Y =C +B D hence Y=C. (B+D) cd ab X X X 10 X X X 0

6 5. a.simplify the following expression using Quine-McClusky Method(6 Marks) F(W,X,Y,Z) = Σ m(1,3,6,7,8,9,10,12,13,14) List the minterm in increasing order of their index No WXYZ Index Stage1 No WXYZ Index Stage2 No WXYZ Index 1, , , , , , , , , , , , Stage3 WXYZ 8,9,12, ,10,12, Prime Implicants: W X Z,XYZ,W YZ,W XY,XYZ,WY,WZ Prime Implicant Table MTs PIs 1,3 W X Z X X 3,7 W YZ X X 6,7 W XY X X 6,14 XYZ X X F(W,X,Y,Z) = WY +WZ +W X Z+W XY

7 5b.Write the Verilog HDL code (using structural model) for the Boolean function Y=NAND(Y1,Y2);where Y1=A+B and Y2=B+C (4Marks) General definition modulemodule_name ( port_list ); port declarations; variable declaration; description of behavior endmodule Example moduletestcircuit (Y,A, B,C); input A, B,C; output Y; wire Y1,Y2; or g1(y1,a,b); or g2(y2,b,c); nand(y,y1,y2); endmodule 6. What are static hazards? Explain with an example. (10Marks)

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The