Logic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson
|
|
|
- Amanda Malone
- 6 years ago
- Views:
Transcription
1 Logic Deign CS 270: Mathematical Foundation of Computer Science Jeremy Johnon
2 Logic Deign Objective: To provide an important application of propoitional logic to the deign and implification of logic circuit. 2
3 Topic Logic gate and, or, inverter nand Logic circuit Encoder, decoder, multiplexor Simplification of logic circuit Full adder Implementation of a imple proceor 3
4 Logic Circuit A ingle line labeled x i a logic circuit. One end i the input and the other i the output. If A and B are logic circuit o are: and gate A B or gate A B inverter (not) A 4
5 Cacaded and gate Multi-Input Gate A B C D ((A B) C) D (A B) (C D) A (B (C D)) A B A B C D C D A B C D 5
6 Logic Circuit Given a boolean expreion it i eay to write down the correponding logic circuit Here i the circuit for the original multiplexor expreion x 0 x 1 6
7 Logic Circuit Here i the circuit for the implified multiplexor expreion x 0 x 1 7
8 Nand Nand negation of the conjunction operation: x y x y A nand gate i an inverted and gate: 8
9 Implementing Logic Gate with Tranitor +V +V gate output A B A NAND B ground ground A Tranitor NOT Gate A Tranitor NAND Gate 9
10 Decoder A decoder i a logic circuit that ha n input (think of thi a a binary number) and 2 n output. The output correponding to the binary input i et to 1 and all other output are et to 0. d 0 b 0 d 1 b 1 d 2 d 3 10
11 Encoder An encoder i the oppoite of a decoder. It i a logic circuit that ha 2 n input and n output. The output equal to the input line (in binary) that i et to 1 i et to 1. d 0 d 1 b 0 d 2 d 3 b 1 11
12 Multiplexor A multiplexor i a witch which route n input to one output. The input i elected uing a decoder. d 0 d 1 d 2 d
13 XOR One or the other, but not both Notation for circuit: x y x y x y x y
14 Full Adder Ued to add to binary number tored a an array of bit uing carry ripple addition CarryIn Three binary input a, b and CarryIn Two binary output Sum and CarryOut uch that a + b + CarryIn = 2*CarryOut + Sum Carry 110 A 101 B 111 A+B = 1100 a b CarryOut Sum 14
15 Exercie Derive a truth table for the output bit (Sum and CarryOut) of a full adder. Uing the truth table derive a um of product expreion for Sum and CarryOut. Draw a circuit for thee expreion. Uing propertie of Boolean algebra implify your expreion. Draw the implified circuit. CarryIn a b Sum CarryOut 15
16 Building a Computer from Logic Gate Objective: To develop a imple model of a computer and it execution that i capable of executing RAM program. To introduce the concept of abtraction in computer deign. The model will be given chematically with timing equence. RAL intruction will be implemented uing microintruction decribed in a notation called Regiter Tranfer Language (RTL). The control logic for implementing microintruction will be decribed at the gate level. Reference: Dewdney, The New Turing Omnibu (Chapter 48). Lec 2 Sytem Architecture 16
17 SCRAM A Simple but Complete Random Acce Machine. Thi computer can execute RAL intruction. 8-bit word 16 word memory (4 addre bit) Intruction (4 bit opcode, 4 bit operand) 7 regiter PC (program counter) IR (intruction regiter - IR(C) = intruction code, IR(O) = operand MAR (memory addre regiter) MBR (memory buffer regiter) AC (accumulator) AD (regiter for addition internal to the ALU - arithmetic logic unit) Driven by the CLU (control logic unit) A timer T generate pule that are decoded into eparate input line to the CLU Lec 2 Sytem Architecture 17
18 Fetch and Execute A cycle of operation conit of two tage The fetch cycle get the next executable intruction and load it into the IR The execute cycle perform the intruction in the IR The fetch and execute cycle are written a a equence of micro-intruction decribed in a notation called Regiter Tranfer Language (RTL) Important: thi machine ue a timer T that tick everal time per each of the two cycle; therefore, the fetch and execute cycle conit of everal clock cycle. Lec 2 Sytem Architecture 18
19 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC MUX CLEAR AC ALU AD MUX 0 1 Decoder T Lec 2 Sytem Architecture 19
20 Intruction Opcode LDA 0001 X; Load content of memory addre X into the AC LDI 0010 X; Indirectly load content of addre X into the AC STA 0011 X; Store content of AC at memory addre X STI 0100 X; Indirectly tore content of AC at addre X ADD 0101 X; Add content of addre X to the AC SUB 0110 X; Subtract content of addre X from the AC JMP 0111 X; Jump to the intruction labeled X JMZ 1000 X; Jump to intruction X if the AC contain 0 Lec 2 Sytem Architecture 20
21 Microprogram Fetch cycle t 0 : MAR PC t 1 : MBR M; PC PC + 1 t 2 : IR MBR Execute cycle (LDA) q 1 t 3 : MAR IR(O) q 1 t 4 : MBR M q 1 t 5 : AC MBR Lec 2 Sytem Architecture 21
22 Microprogram Execute cycle (LDI) q 2 t 3 : MAR IR(O) q 2 t 4 : MBR M q 2 t 5 : MAR MBR q 2 t 6 : MBR M q 2 t 7 : AC MBR Execute cycle (ADD) q 5 t 3 : MAR IR(O) q 5 t 4 : MBR M q 5 t 5 : AD MBR q 5 t 6 : AD AD + AC q 5 t 7 : AC AD Lec 2 Sytem Architecture 22
23 Microprogram Execute cycle (JMP) PC relative addreing q 7 t 3 : AC PC q 7 t 4 : AD AC q 7 t 5 : AC IR(0) q 7 t 6 : AD AD + AC q 7 t 7 : AC AD q 7 t 8 : PC AC Execute cycle (JMP) abolute addreing q 7 t 3 : AC IR(0) q 7 t 4 : PC AC Lec 2 Sytem Architecture 23
24 Control Logic for the Fetch Cycle t 0 : MAR PC t 1 : MBR M; PC PC + 1 t 2 : IR MBR t 0 x 10 x 10 x 4 t 1 x 7 x 2 x 5 x 13 t 2 x 1 Lec 2 Sytem Architecture 24
25 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD MAR PC MUX 0 1 Lec 2 Sytem Architecture 25
26 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD MUX 0 1 MBR M; PC PC + 1 Lec 2 Sytem Architecture 26
27 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD MUX 0 1 IR MBR Lec 2 Sytem Architecture 27
28 Logic for Loading the Accumulator q 1 t 3 x 10 x 10 MAR IR(0) x 4 x 2 t 4 x 7 MBR M x 5 t 5 x 11 x 11 x 12 AC MBR Lec 2 Sytem Architecture 28
29 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD MUX 0 1 MAR IR(0) Lec 2 Sytem Architecture 29
30 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD MBR M MUX 0 1 Lec 2 Sytem Architecture 30
31 PC INC MAR MUX Memory READ/ WRITE IR(C) Decoder IR(O) MBR MUX 0 1 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 x 1 x 2 x 3 x 4 x 5 CLU t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 Decoder x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 INC T MUX CLEAR AC ALU AD AC MBR MUX 0 1 Lec 2 Sytem Architecture 31
32 CLU Logic Some of the output line from the two previou lide appear in both circuit. It i neceary to have ome logic to connect and coordinate the individual output to the wire leaving the CLU. Lec 2 Sytem Architecture 32
33 Exercie Write microprogram for STA, STI, and JMZ. Implement the microprogram in tandard logic. Deign the portion of the CLU that determine the two output line labeled x 10. Input to thi circuit will be one or both of the line previouly labeled x 10 in the individual circuit for LDA, LDI, and the other circuit. Convert the following program to the equivalent et of binary word, a indicated in thi chapter. Thi i called machine code. Trace the execution of the program by liting the q, t, and x variable. LDA 1 ADD 2 STA 3 Lec 2 Sytem Architecture 33
Enrico Nardelli Logic Circuits and Computer Architecture
Enrico Nardelli Logic Circuits and Computer Architecture Appendix B The design of VS0: a very simple CPU Rev. 1.4 (2009-10) by Enrico Nardelli B - 1 Instruction set Just 4 instructions LOAD M - Copy into
UNIVERSITY OF WISCONSIN MADISON
CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,
Combinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
CMP 334: Seventh Class
CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative
ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
Numbers and Arithmetic
Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu
CPSC 3300 Spring 2017 Exam 2
CPSC 3300 Spring 2017 Exam 2 Name: 1. Matching. Write the correct term from the list into each blank. (2 pts. each) structural hazard EPIC forwarding precise exception hardwired load-use data hazard VLIW
Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
Computer organization
Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java High-level language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data
Solutions - Final Exam (Online Section) (Due Date: December 11th by 10:00 am) Clarity is very important! Show your procedure!
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 Solution - Final am (Online Section) (Due Date: December th by : am) Clarity i very important! Show
Floating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015.
LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Note - Unit 7 INTRODUCTION TO DIGITAL SYSTM DSIGN DIGITAL SYSTM MODL FSM + Datapath Circuit:
Fundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
CS/COE0447: Computer Organization and Assembly Language
CS/COE0447: Computer Organization and Assembly Language Logic Design Introduction (Brief?) Appendix B: The Basics of Logic Design Dept. of Computer Science Logic design? Digital hardware is implemented
University of Guelph School of Engineering ENG 2410 Digital Design Fall There are 7 questions, answer all questions.
Final Examination Instructor: Shawki M. Areibi Co-examiner: Medhat Moussa. Location: UOG Date: Wednesday, December 5th, 2007 Time: 8:30-10:30 AM Duration: 2 hours. Type: R Closed Book. Instructions: University
Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
Figure 4.9 MARIE s Datapath
Term Control Word Microoperation Hardwired Control Microprogrammed Control Discussion A set of signals that executes a microoperation. A register transfer or other operation that the CPU can execute in
Logic and Boolean algebra
Computer Mathematics Week 7 Logic and Boolean algebra College of Information Science and Engineering Ritsumeikan University last week coding theory channel coding information theory concept Hamming distance
Design of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)
COSC 243 Introduction to Logic And Combinatorial Logic 1 Overview This Lecture Introduction to Digital Logic Gates Boolean algebra Combinatorial Logic Source: Chapter 11 (10 th edition) Source: J.R. Gregg,
Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers
-2. -2.2 piral / Unit 2 Basic Boolean Algebra Logic Functions Decoders Multipleers Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name eamples of each.
Numbers and Arithmetic
Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu
EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
Adder Circuits Ivor Page 1
Adder Circuit Adder Circuit Ivor Page 4. The Ripple Carr Adder The ripple carr adder i probabl the implet parallel binar adder. It i made up of k full-adder tage, where each full-adder can be convenientl
CS61C : Machine Structures
CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS
Spiral 2-1. Datapath Components: Counters Adders Design Example: Crosswalk Controller
2-. piral 2- Datapath Components: Counters s Design Example: Crosswalk Controller 2-.2 piral Content Mapping piral Theory Combinational Design equential Design ystem Level Design Implementation and Tools
Overview. Multiplexor. cs281: Introduction to Computer Systems Lab02 Basic Combinational Circuits: The Mux and the Adder
cs281: Introduction to Computer Systems Lab02 Basic Combinational Circuits: The Mux and the Adder Overview The objective of this lab is to understand two basic combinational circuits the multiplexor and
Lecture 4 Modeling, Analysis and Simulation in Logic Design. Dr. Yinong Chen
Lecture 4 Modeling, Analysis and Simulation in Logic Design Dr. Yinong Chen The Engineering Design Process Define Problem and requirement Research Define Alternative solutions CAD Modeling Analysis Simulation
ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates
ECE 250 / CPS 250 Computer Architecture Basics of Logic Design Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Andrew Hilton (Duke), Alvy Lebeck (Duke) Benjamin Lee (Duke), and Amir
ECE/CS 250 Computer Architecture
ECE/CS 250 Computer Architecture Basics of Logic Design: Boolean Algebra, Logic Gates (Combinational Logic) Tyler Bletsch Duke University Slides are derived from work by Daniel J. Sorin (Duke), Alvy Lebeck
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS
Systems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
Hakim Weatherspoon CS 3410 Computer Science Cornell University
Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. memory inst 32 register
Lecture 18: Datapath Functional Units
Lecture 8: Datapath Functional Unit Outline Comparator Shifter Multi-input Adder Multiplier 8: Datapath Functional Unit CMOS VLSI Deign 4th Ed. 2 Comparator 0 detector: A = 00 000 detector: A = Equality
Sample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
Processor Design & ALU Design
3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of
ALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 5 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.
![XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.](/thumbs/81/84726747.jpg "XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.")
2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two
ECE290 Fall 2012 Lecture 22. Dr. Zbigniew Kalbarczyk
ECE290 Fall 2012 Lecture 22 Dr. Zbigniew Kalbarczyk Today LC-3 Micro-sequencer (the control store) LC-3 Micro-programmed control memory LC-3 Micro-instruction format LC -3 Micro-sequencer (the circuitry)
UNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018
DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b
CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh
CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process
We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 3 1 Logistics If you cannot login to MarkUs, email me your UTORID and name. Check lab marks on MarkUs, if it s recorded wrong, contact Larry within a week after the lab. Quiz 1 average: 86%
Arithmetic and Logic Unit First Part
Arithmetic and Logic Unit First Part Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ALU1-1 Typical
Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
Unit 8A Computer Organization. Boolean Logic and Gates
Unit 8A Computer Organization Boolean Logic and Gates Announcements Bring ear buds or headphones to lab! 15110 Principles of Computing, Carnegie Mellon University - CORTINA 2 Representing and Manipulating
Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173
Propositional Logic CSC 17 Propositional logic mathematical model (or algebra) for reasoning about the truth of logical expressions (propositions) Logical expressions propositional variables or logical
Chapter 5. Digital systems. 5.1 Boolean algebra Negation, conjunction and disjunction
Chapter 5 igital systems digital system is any machine that processes information encoded in the form of digits. Modern digital systems use binary digits, encoded as voltage levels. Two voltage levels,
Lecture 12: Datapath Functional Units
Lecture 2: Datapath Functional Unit Slide courtey of Deming Chen Slide baed on the initial et from David Harri CMOS VLSI Deign Outline Comparator Shifter Multi-input Adder Multiplier Reading:.3-4;.8-9
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Decoders and Encoders CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
CHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables
UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1
Chapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
Combinational Logic Trainer Lab Manual
Combinational Logic Trainer Lab Manual Control Inputs Microprocessor Data Inputs ff Control Unit '0' Datapath MUX Nextstate Logic State Memory Register Output Logic Control Signals ALU ff Register Status
CSE 200 Lecture Notes Turing machine vs. RAM machine vs. circuits
CSE 200 Lecture Notes Turing machine vs. RAM machine vs. circuits Chris Calabro January 13, 2016 1 RAM model There are many possible, roughly equivalent RAM models. Below we will define one in the fashion
ECE/CS 250: Computer Architecture. Basics of Logic Design: Boolean Algebra, Logic Gates. Benjamin Lee
ECE/CS 250: Computer Architecture Basics of Logic Design: Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Alvin Lebeck, Daniel Sorin, Andrew Hilton, Amir Roth, Gershon Kedem Admin
UNIVERSITY OF CALIFORNIA, RIVERSIDE
Final Page of UNIVERITY OF CLIFORNI, RIVERIDE Computer cience Department and Electrical Engineering Department C/EE20 Logic Design Final December, 2000 50 Name: olution Key tudent ID#: Please print legibly
Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
Hardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
Philadelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
Adders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
DE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
Computer Science. 19. Combinational Circuits. Computer Science COMPUTER SCIENCE. Section 6.1.
COMPUTER SCIENCE S E D G E W I C K / W A Y N E PA R T I I : A L G O R I T H M S, M A C H I N E S, a n d T H E O R Y Computer Science Computer Science An Interdisciplinary Approach Section 6.1 ROBERT SEDGEWICK
ENGG 1203 Tutorial. Solution (b) Solution (a) Simplification using K-map. Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives
ENGG 23 Tutorial Simplification using K-map Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives Apply Karnaugh map for logic simplification Design a finite state machine News HW
Hardware Implementation of Canonic Signed Digit Recoding
IOSR Journal of VLSI and Signal Proceing (IOSR-JVSP) Volume 6, Iue 2, Ver. I (Mar. -Apr. 2016), PP 11-15 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iorjournal.org Hardware Implementation of Canonic
Computer Science. Questions for discussion Part II. Computer Science COMPUTER SCIENCE. Section 4.2.
COMPUTER SCIENCE S E D G E W I C K / W A Y N E PA R T I I : A L G O R I T H M S, T H E O R Y, A N D M A C H I N E S Computer Science Computer Science An Interdisciplinary Approach Section 4.2 ROBERT SEDGEWICK
System Data Bus (8-bit) Data Buffer. Internal Data Bus (8-bit) 8-bit register (R) 3-bit address 16-bit register pair (P) 2-bit address
Intel 8080 CPU block diagram 8 System Data Bus (8-bit) Data Buffer Registry Array B 8 C Internal Data Bus (8-bit) F D E H L ALU SP A PC Address Buffer 16 System Address Bus (16-bit) Internal register addressing:
CS/COE0447: Computer Organization
Logic design? CS/COE0447: Computer Organization and Assembly Language Logic Design Review Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values:
For smaller NRE cost For faster time to market For smaller high-volume manufacturing cost For higher performance
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]
Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.
Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits
Combinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
CS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Logic Design Review Sangyeun Cho Dept. of Computer Science Logic design? Digital hardware is implemented by way of logic design Digital circuits
Project Two RISC Processor Implementation ECE 485
Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor
ELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
Practice Homework Solution for Module 4
Practice Homework Solution for Module 4 1. Tired of writing the names of those you want kicked off the island on cards, you wish to modernize the voting scheme used on Digital Survivor. Specifically, you
Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control
Logic and Computer Design Fundamentals Chapter 8 Sequencing and Control Datapath and Control Datapath - performs data transfer and processing operations Control Unit - Determines enabling and sequencing
Lecture 5: Arithmetic
Lecture 5: Arithmetic COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 5 Binary Representation of Integers Two physical states: call these 1 and
Basic Computer Organization and Design Part 3/3
Basic Computer Organization and Design Part 3/3 Adapted by Dr. Adel Ammar Computer Organization Interrupt Initiated Input/Output Open communication only when some data has to be passed --> interrupt. The
Adders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
Computer Organization: Boolean Logic
Computer Organization: Boolean Logic Representing and Manipulating Data Last Unit How to represent data as a sequence of bits How to interpret bit representations Use of levels of abstraction in representing
CSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
Review for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
Lecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,
CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
[2] Predicting the direction of a branch is not enough. What else is necessary?
![[2] Predicting the direction of a branch is not enough. What else is necessary?](/thumbs/74/69859984.jpg "[2] Predicting the direction of a branch is not enough. What else is necessary?")
[2] When we talk about the number of operands in an instruction (a 1-operand or a 2-operand instruction, for example), what do we mean? [2] What are the two main ways to define performance? [2] Predicting
Boolean Algebra, Gates and Circuits
Boolean Algebra, Gates and Circuits Kasper Brink November 21, 2017 (Images taken from Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.) Outline Last week: Von
A Second Datapath Example YH16
A Second Datapath Example YH16 Lecture 09 Prof. Yih Huang S365 1 A 16-Bit Architecture: YH16 A word is 16 bit wide 32 general purpose registers, 16 bits each Like MIPS, 0 is hardwired zero. 16 bit P 16
Every time has a value associated with it, not just some times. A variable can take on any value within a range
Digital Logic Circuits Binary Logic and Gates Logic Simulation Boolean Algebra NAND/NOR and XOR gates Decoder fundamentals Half Adder, Full Adder, Ripple Carry Adder Analog vs Digital Analog Continuous»
CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)
CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3) Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000):
KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
A crash course in Digital Logic
crash course in Digital Logic Computer rchitecture 1DT016 distance Fall 2017 http://xyx.se/1dt016/index.php Per Foyer Mail: per.foyer@it.uu.se Per.Foyer@it.uu.se 2017 1 We start from here Gates Flip-flops