# CS61C : Machine Structures

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1 CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look Andy Carle CS 61C L15 Blocks (2) Review (1/3) (2/3): Circuit & Algebraic Simplification Use this table and techniques we learned to transform from 1 to another CS 61C L15 Blocks (3) CS 61C L15 Blocks (4) (3/3):Laws of Boolean Algebra CL Blocks Let s use our skills to build some CL blocks: Multiplexer (mux) Adder ALU CS 61C L15 Blocks (5) CS 61C L15 Blocks (6)

2 CS 61C L15 Blocks (7) Data Multiplexor (here 2-to-1, n-bit-wide) N instances of 1-bit-wide mux mux CS 61C L15 Blocks (8) How do we build a 1-bit-wide mux? 4-to-1 Multiplexor? CS 61C L15 Blocks (9) CS 61C L15 Blocks () An Alternative Approach Arithmetic and Logic Unit Most processors contain a logic block called Arithmetic/Logic Unit (ALU) We ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR Hierarchically! CS 61C L15 Blocks (11) CS 61C L15 Blocks (12)

3 CS 61C L15 Blocks (13) Our simple ALU Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we ve seen before Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer CS 61C L15 Blocks (14) N 1-bit adders 1 N-bit adder Adder/Subtracter One-bit adder LSB b CS 61C L15 Blocks (15) CS 61C L15 Blocks (16) Adder/Subtracter One-bit adder (1/2) Adder/Subtracter One-bit adder (2/2) CS 61C L15 Blocks (17) CS 61C L15 Blocks (18)

4 CS 61C L15 Blocks (19) What about overflow? What about overflow? What op? Consider a 2-bit signed # & overflow: = or = only 00 = 0 NOTHING! ± # 01 = only Highest adder C 1 = Carry-in = C in, C 2 = Carry-out = C out No C out or C in NO overflow! C in, and C out NO overflow! C in, but no C out A,B both > 0, overflow! C out, but no C in A,B both < 0, overflow! Consider a 2-bit signed # & overflow: = or = only 00 = 0 NOTHING! ± # 01 = only Overflows when C in, but no C out A,B both > 0, overflow! C out, but no C in A,B both < 0, overflow! CS 61C L15 Blocks (20) Extremely Clever Subtractor Administrivia We re now halfway through the semester yikes HW 45 Due Monday Proj2 coming Logisim! CS 61C L15 Blocks (21) CS 61C L15 Blocks (22) State Circuits Overview State circuits have feedback, e.g. in0 in1 Output is function of inputs + fed-back signals. Feedback signals are the circuit's state. What aspects of this circuit might cause complications? CS 61C L15 Blocks (23) Combi- lab 12 national counter Logic out0 out1 A simpler state circuit: two inverters 0 1! When started up, it's internally stable. Provide an or gate for coordination: 01 S OR What's the result? How do we set to 0? CS 61C L15 Blocks (24)

5 CS 61C L15 Blocks (25) S An R-S latch (cross-coupled NOR gates) S means set (to 1), R means reset (to 0). 01 OR _ OR Hold! R Adding gives standard RS-latch: Truth table S R 0 0 hold (keep value) unstable A B N O R An R-S latch (in detail) A B N O R CS 61C L15 Blocks (26) Truth table _ S R (t+ t) 0 0 hold 0 1 hold 1 0 reset 0 1 reset 1 1 set 1 1 set x x unstable x x unstable Controlling R-S latch with a clock Can't change R and S while clock is active. A B N O R R' clock' S' Clocked latches are called flip-flops. R S ' D flip-flop are what we really use Inputs C (clock) and D. When C is 1, latch open, output = D (even if it changes, transparent latch ) When C is 0, latch closed, output = stored value. C D AN D CS 61C L15 Blocks (27) CS 61C L15 Blocks (28) D flip-flop details We don t like transparent latches We can build them so that the latch is only open for an instant, on the rising edge of a clock (as it goes from 0 1) Edge Detection A B O D C Timing Diagram This is a rising-edge D Flip-Flop When the CLK transitions from 0 to 1 (rising edge) - D; bar not D All other times: ; bar bar CS 61C L15 Blocks (29) CS 61C L15 Blocks (30)

6 CS 61C L15 Blocks (31) Peer Instruction A. Truth table for mux with 4 control signals has 2 4 rows B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T And In conclusion Use muxes to select among input S input bits selects 2S inputs Each input can be n-bits wide, indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1- bit adders with XOR gates on input XOR serves as conditional inverter CS 61C L15 Blocks (32)

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