Processor Design & ALU Design

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3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.

1 3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of Adder Multiplier : Serial, Parallel and Floating Point Processor Design Single Cycle ( Path and Control) Multi cycle ( Path) Pipeline ( Path) Flow of Our Course Understanding of Overall Computer Understanding of an existing processor architecture and Analysis Understanding of CISC to RISC Assembly language program : MIPS and X86 Components of processor : Reg, Mux., Mem, Adder Processor Design : Path and Control Path Processor Design : Analysis and Improvement Processor Design & Design Topic Design Processor Design Design Adder/ Substrator, Multiplier Floating point, (Int/float) Design Processor Design Single Cycle ( Path & Control Path) Multi Cycle (Only Path) Pipelined (Only path) Components for MIPS subset Register Adder Multiplexer Register file Program memory memory Bit manipulation components MIPS Components Register clock

2 3/8/2 MIPS Components Adder offset MIPS Components operation a=b a overflow result b MIPS components Multiplexers MIPS Components register file mux offset Register Number Re Reg Re Reg 2 Registers Write Reg Write data Re Re 2 select Reg Write MIPS Components: Program memory MIPS Components Bit manipulation circuits Address Memory 6 sign xtend shift 2

3 3/8/2 Processor Design Processor Design A simple implementation: Single Cycle path and control Performance considerations Multi cycle design path and control Micro programmed control Exception handling 3 Simple Processor Design MIPS subset for implementation Design overview Division into data path and control Building blocks combinational and sequential Clock and timings Components required for MIPS subset MIPS subset for implementation Arithmetic logic tructions d, sub, and, or, slt Memory reference tructions lw, sw Control flow tructions beq, j Incremental changes in the design to include other tructions will be discussed later Generic Implementation Design overview Use the program counter () to supply truction dress Get the truction from memory Re registers Use the truction to decide exactly what to do Memory Address Reg# Register Reg# FILE Reg# Address Memory 8 3

4 3/8/2 Division into path and Control A Processor Design Method Build the datapath step by step as follows control DATA PATH CONTROLLER status Start with R class tructions Include other tructions one by one Identify control Interconnect datapath and controller MIPS subset for implementation Division into data path and control Arithmetic logic tructions d, sub, and, or, slt Memory reference tructions lw, sw Control flow tructions beq, j control DATA PATH CONTROLLER status path for d,sub,and,or,slt Fetching truction fetch truction dress the register file pass operands to actions passresult to register file required increment Format: d $t, $s, $ op r dst r src r src2 shamt funct

5 3/8/2 Addressing RF Passing operands to [2 2] [2 6] r rd r2 w rd2 [2 2] [2 6] r rd r2 w rd2 Passing the result to RF Incrementing [2 2] [2 6] [ ] r r2 w RF rd rd2 [2 2] [2 6] [ ] r rd r2 w rd2 Lo and Store tructions Adding sw truction format : I Example: lw $t, ($) op r dst r src 6 bit number [2 2] [2 6] [ ] [ ] r rd r2 w rd2 6 rd

6 3/8/2 Adding lw truction Format of beq truction beq I format op rs rt 6 bit number [2 2] [2 6] [ ] [ ] r rd r2 w rd2 6 rd = () SignXtend6to (level*2) Adding beq truction MIPS components bit manipulation circuits 6 sign xtend [2 2] [2 6] [ ] [ ] r rd r2 w rd2 6 rd Shift 2 Format of jump truction Adding j truction j op J format 26 bit number [2 ] 28 [3 28] ja[3 ] = Higher bit Old Level <<2 = bit from 6 bit Level 2 bit = bits [2 2] [2 6] [ ] [ ] r rd r2 w rd2 6 rd 6

7 3/8/2 Control [2 ] 28 [3 28] ja[3 ] jmp Psrc path Control [2 ] [3 26] [3 28] ol ontrol 28 ja[3 ] brn jmp Psrc [2 2] [2 6] [ ] Rdst [ ] RW r rd r2 w rd2 6 3Asrc op Z MW rd MR M2R [2 2] [2 6] [ ] Rdst [ ] [ ] co RW r rd r2 w rd2 6 Asrc 3 op Actrl 2 opc Z MW rd MR M2R Summary Processor designed for {d, sub, and, or, slt, lw, sw, beq, j} Step by step approach S d ih{dd b d l} Started with {d, sub, and, or, slt} Added {sw, lw}, then ded {beq, j} Identified control and connected to a controller (black box). 7

SISD SIMD. Flynn s Classification 8/8/2016. CS528 Parallel Architecture Classification & Single Core Architecture C P M

SISD SIMD. Flynn s Classification 8/8/2016. CS528 Parallel Architecture Classification & Single Core Architecture C P M 8/8/26 S528 arallel Architecture lassification & Single ore Architecture arallel Architecture lassification A Sahu Dept of SE, IIT Guwahati A Sahu Flynn s lassification SISD Architecture ategories M SISD