ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015.

Size: px

Start display at page:

Download "ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015."

Baldwin Ray
6 years ago
Views:

LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Note - Unit 7 INTRODUCTION TO DIGITAL SYSTM DSIGN DIGITAL SYSTM MODL FSM + Datapath

1 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Note - Unit 7 INTRODUCTION TO DIGITAL SYSTM DSIGN DIGITAL SYSTM MODL FSM + Datapath Circuit: DATAPATH CIRCUIT Input clock FINIT STAT MACHIN CONTROL CIRCUIT Output XAMPL: CAR LOT COUNTR photo receptor If A = No light received (car obtructing LD A) If B = No light received (car obtructing LD B) B A If car enter the lot, the following equence (A B) mut be followed: If car leave the lot, the following equence (A B) mut be followed: A car might tay in a tate for many cycle ince the car peed i very large compared to that of the clock frequency. DIGITAL SYSTM (FSM + Datapath circuit) Uually, when (aynchronou clear) and clock are not drawn, they are implied. A B FINIT STAT MACHIN ud ud Q clock CONTROL CIRCUIT -bit counter DATAPATH CIRCUIT Intructor: Daniel Llamocca

2 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Finite State Machine (FSM): A B/ ud = / / / / / / / / /,,/ S S3 S S5 / / / / / / / / / / / / / / / S6 / / S7 S8 / / / Algorithmic State Machine (ASM) chart: S = = no ye S3 S6 S S7 S S8, ud Intructor: Daniel Llamocca

3 clr LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: ACCUMULATOR DIGITAL SYSTM (FSM + Datapath circuit) clr: Synchronou clear. If = and clr =, then the output bit of the regiter are et to ero. Din 8 D Q 8 ign extenion + D Q Dout retart i FINIT STAT MACHIN clr Finite State Machine (FSM): retart/i clr = / / X/ S / / X/ Algorithmic State Machine (ASM): S = retart i, clr i i, clr retart i 3 Intructor: Daniel Llamocca

4 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: 7-SGMNT SRIALIZR DIGITAL SYSTM (FSM + Datapath circuit) Mot FPGA Development board have a number of 7-egment diplay (e.g.,, 8). However, only one can be ued at a time. If we want to diplay four digit (input A, B, C, D), we can deign a erialier that will only how one digit at a time on the 7-egment diplay. Since only one 7-egment diplay can be ued at a time, we need to erialie the four BCD output. In order for each digit to appear bright and continuouly illuminated, each digit i illuminated for m every m (i.e. a digit i un-illuminated for 3 m and illuminated for m). Thi i taken care of by feeding the output '' of the counter to. to the enable input of the FSM. Thi way, tate tranition only occur each.. In the figure, the enable ignal for the four 7-egment diplay are active low (thi i uually the cae). A B C D 3 BCD to 7 egment decoder 7 Counter (.) -to- decoder buf buf(3) buf() buf() buf() FINIT STAT MACHIN Algorithmic State Machine (ASM) chart: Thi i a Moore-type FSM. = S S3 S Intructor: Daniel Llamocca

5 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: BIT-COUNTING CIRCUIT SQUNTIAL ALGORITHM C while A if a = then C C + end if right hift A end while DIGITAL SYSTM (FSM + Datapath circuit) clr: Synchronou clear. In thi cae, if clr =, the count i initialied to ero (here, we do not need C to be ). Data _l _r din _l Parallel Acce Right Shift (MSB to LSB) _l = Load _l = Shift n A n C Q m clr_c C clr counter: m bit m = ceil(log(n)) + a FINIT STAT MACHIN done Algorithmic State Machine (ASM) chart: S = clr_c _r, _l _r S3 done a C 5 Intructor: Daniel Llamocca

6 _G O_G _ext _R O_R _R O_R _R O_R _R3 O_R3 op _A LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: SIMPL PROCSSOR DIGITAL SYSTM (FSM + Datapath circuit) Data_in n D Q n Data BUS R R R R3 A B ALU G w fun 7 CONTROL CIRCUIT done Operation: very time w = '', we grab the intruction from fun and execute it: funq = f f f Ry Ry Rx Rx f Operation Function Load Rx, Data Rx Data Move Rx, Ry Rx Ry Add Rx, Ry Rx Rx + Ry Sub Rx, Ry Rx Rx - Ry Not Rx Rx NOT (Rx) And Rx, Ry Rx Rx AND Ry Or Rx, Ry Rx Rx OR Ry Xor Rx, Ry Rx Rx XOR Ry 6 Intructor: Daniel Llamocca

7 _fun _A _G op O_G _ext LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Control Circuit: fun _fun 7 D Q 7 funq Rx Rx x DCODR with enable 3 _R _R _R _R3 Ry Rx o o DCODR with enable 3 O_R O_R O_R O_R3 funq = f f f Ry Ry Rx Rx x o o w f 3 FSM done Arithmetic-Logic Unit (ALU): op Operation Function Unit y <= A y <= A + y <= A - Tranfer A Increment A Decrement A y <= B Tranfer B y <= B + Increment B Arithmetic y <= B y <= A + B y <= A B Decrement B Add A and B Subtract B from 'A' y <= not A y <= not B y <= A AND B y <= A OR B y <= A NAND B y <= A NOR B y <= A XOR B y <= A XNOR B Complement A Complement B AND OR NAND NOR XOR XNOR Logic 7 Intructor: Daniel Llamocca

8 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Algorithmic State Machine (ASM): S = w _fun _ext, x done f o, x done o, o _A o, o _A o, o _A o, o _A o, o _A o, o _A S3a Sa S5a S6a S7a S8a o, _G op o, _G op _G op o, _G op o, _G op o, _G op S3b Sb S5b S6b S7b S8b O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done 8 Intructor: Daniel Llamocca

9 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: ARBITR CIRCUIT DIGITAL SYSTM (FSM + Datapath circuit) Three device can requet acce to a certain reource at any time (example: acce to a bu made of tri-tate buffer, only one tri-tate buffer can be enabled at a time). The FSM can only grant acce to one device at a time.there hould be a priority level among device. If the FSM grant acce to one device, one mut wait until the requet ignal to that device i deaerted (i.e. et to ero) before granting acce to a different device. DVIC req priority grant DVIC grant req clock r r r3 FINIT STAT MACHIN g g g3 DVIC 3 req3 CONTROL CIRCUIT grant3 Algorithmic State Machine (ASM) chart: S = g,g,g3 r r r 3 S3 S g g g3 r r r 3 9 Intructor: Daniel Llamocca

LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: DISPLAYING PATTRNS ON 7-SGMNT DISPLAYS Different pattern are hown baed on the

10 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: DISPLAYING PATTRNS ON 7-SGMNT DISPLAYS Different pattern are hown baed on the elector el ignal. Two 7-egment diplay are ued. top input: If it i aerted (top = ), the light pattern freee. The input x elect the rate of change (every.5,.,.5, or.5 econd). eg[7..] : el eg x 5 top? 3 el[..] clock DIGITAL SYSTM (FSM + Datapath circuit) x top clock Q?? counter (.5) Q?? el FINIT STAT MACHIN deg 8 g D Q On the NXYS, only one 7-egment diplay can be ued at a time 7 counter (.) 3 Counter (.) Q?? FINIT STAT MACHIN -to- decoder buf buf() buf() counter (.5) Q?? x = Light change every.5 x = Light change every. x = Light change every.5 x = Light change every.5 counter (.5) Intructor: Daniel Llamocca

11 LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Algorithmic State Machine (ASM) chart: S = el deg, g deg, g deg, g deg, g S5 S8 S deg, g deg, g deg, g deg, g S3 S6 S9 deg, g deg, g deg, g deg, g S S7 S S3 deg, g deg, g deg, g deg, g Algorithmic State Machine (ASM) chart: Thi i the FSM that control the output MUX S = Intructor: Daniel Llamocca

12 A LA B LB P clrp LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 XAMPL: SRIAL MULTIPLIR SQUNTIAL ALGORITHM P, Load A,B while B if b = then P P + A end if left hift A right hift B end while DIGITAL SYSTM (FSM + Datapath circuit) Note that thi algorithm can alo be run on a imple proceor. Here, we ue dedicated circuitry. clr: Synchronou clear. In thi cae, if clr = and =, the regiter content are initialied to. ".."&DataA DataB n n LA A din _l A LB B din _l B Parallel Acce _l = Load _l = Shift Shift-left n n Shift-right b FSM done P clrp clr + P n b n Algorithmic State Machine (ASM) chart: S clrp P = LA, A, LB, B A, B S3 done b P Intructor: Daniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 7 DATAPATH CIRCUIT

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 7 DATAPATH CIRCUIT LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 Note - Unit 7 INTRODUCTION TO DIGITL SYSTM DSIGN DIGITL SYSTM MODL FSM + Datapath Circuit: DTPTH CIRCUIT Input reetn