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7 EE457 Home work #1 Review of EE254L material 3. Datapath and control design: You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a complete data path. Notice that you can bring either P or Q on bus #1 (B_ONE) or bus #2 (B_TWO). SMALL_REG is only tied to B_ONE where as BIG_REG is only tied to B_TWO state state machine Complete the state diagram below by writing state transition conditions. /RESET 1 PQL Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG. START I Initial START 1 CPQ Compare P with Q on B_ONE on B_TWO QPL Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG Complete the one-hot implementation of the above 4-state state machine on page 3. Before you produce the outputs, answer the following questions Can we say that whenever we put P or Q on one of the two buses, we may put the other on the other bus? YES / NO Can we say that, in the initial state, we may drive the buses even though it is not necessary? YES / NO Can we say that we either load both SMALL_REG and BIG_REG or load none? YES / NO Complete the waveform on page 4 EE457 Homework 1 C Copyright 2004 Gandhi Puvvada

11 3.2 3-state state machine The state machine design in 1.1 above is a (Mealy / Moore) as the outputs generated are not influenced by the inputs. The outputs are completely determined by the current state. Let us now reduce the states by combining CPQ and PQL into CPQL compare and load. The load operation is conditional in the CPQL state as can be seen below. This 3-state state machine is a (Mealy / Moore). Complete the state diagram below. /RESET START I Initial START 1 CPQL Compare P (on B_ONE) with Q (on B_TWO). If appropriate Load P (from B_ONE) into Small. Load Q (from B_TWO) into BIG. QPL Load Q (from B_ONE) into Small. Load P (from B_TWO) into BIG Complete the one-hot implementation of the 3-state state machine on page Complete the waveform on page 7. EE457 Homework 1 C Copyright 2004 Gandhi Puvvada

19 ee102_midterm2_sp2005.fm The previous two design are again given below with the VDD/GND connections removed. Now again build two non-inverting 2-to-1 muxes with low active enable by completing the designs. You can use additional inverters if you need. Are the two designs functionally identical (meaning one can be used to replace the other)? YES / NO I0 /I0 Y /Y I1 /I1 S VDD S 2 ( = 72 points) 50 min. Small System Design: Find the smallest number between A and B which is evenly divisible by (decimal 20). The range of your search is A to B, with both A and B included. A and B are two 7 bit binary numbers. A is always less than B. Since twenty is four times five (20 = 4 x 5), both 4 and 5 should divide the number evenly. A binary number divisible by 4 will have its two least significant bits zeros. If you find the number, you go to the FND (FND = Found) state, otherwise you go to NSN (NSN = No Such Number) state. Algorithm: Accept Ain into A and Bin into B. A = A 6 A 5 A 4 A 3 A 2 A 1 A 0. Let us treat this 7-bit register A as actually made up of a 5-bit register Au (A upper) holding the upper 5 bits and a 2- bit register Al (A lower) holding the lowest 2 bits. Since we are looking for a number divisible by twenty, we will start with A 6 A 5 A 4 A 3 A (upper five bits concatenated with two zeros) which is divisible by 4. Before checking to see if it is also divisible by 5, we need to see if the A 1 A 0 are actually two zeros or anything other than two zeros. If they are two zeros, then A 6 A 5 A 4 A 3 A (symbolically written as Au00) is in fact A itself and can be tested for divisibility by 5. Otherwise, we want to increment this 7-bit number Au00 (A 6 A 5 A 4 A 3 A 2 0 0) by 4 (=100), which is same as incrementing the 5-bit number Au (A 6 A 5 A 4 A 3 A 2 ) by 1 (Au <= Au +1). We then test to see if the resulting 7-bit number Au00 is divisible by 5. If we fail, we increment the Au by 1 again. Of course, every time after incrementation, we need to see if Au has exceeded Bu. In fact we discard the lower two bits of B and hold only B 6 B 5 B 4 B 3 B 2 in Bu. So the comparison is actually a 5-bit comparison between Au (A 6 A 5 A 4 A 3 A 2 ) and Bu (B 6 B 5 B 4 B 3 B 2 ). To see if Au00 (A 6 A 5 A 4 A 3 A 2 0 0) is divisible by 5 (= ), we convey Au00 to a divider into its X register. The divider repetitively subtracts 5 (X <= X- 5) until a decision can be reached. Note that we do not need to record the quotient. We do not need the exact reminder also. As long as we know that X is evenly divisible by 5 or not, it is enough. For example, if the remaining X is only a 5, we do not need to wait another clock doing 5-5 = 0 before we can conclude. So, perhaps X = 5 is an exit condition. 4 pts 2.1 Example: A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 = = 41 decimal, B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 = = 75 decimal. After chopping off the least significant two bits, we have A 7 A 6 A 5 A 4 A 3 A 2 = and 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

20 ee102_midterm2_sp2005.fm B 7 B 6 B 5 B 4 B 3 B 2 = Since A 1 A 0 =/= 0 0, let us increment A 7 A 6 A 5 A 4 A 3 A 2 by 1 to and try to see (i) if exceeded (ii) if (44 decimal) is divisible by 5. We know that is the smallest number between and which is divisible by In this example how many different Au00 values are tested to see if they are actually divisible by 5 10? What are they? 44, 18 pts 2.2 After reading the datapath and completing the state diagram later in this question, return to this question. Consider the three cases. Assume that START and ACK are active all the time. (i) A 6 A 5 A 4 A 3 A 2 A 1 A 0 = = 14 decimal, B 6 B 5 B 4 B 3 B 2 B 1 B 0 = = 75 decimal (ii) A 6 A 5 A 4 A 3 A 2 A 1 A 0 = = 19 decimal, B 6 B 5 B 4 B 3 B 2 B 1 B 0 = = 75 decimal (iii) A 6 A 5 A 4 A 3 A 2 A 1 A 0 = = 30 decimal, B 6 B 5 B 4 B 3 B 2 B 1 B 0 = = 31 decimal Waveforms for item (i) has been completed. You need to complete waveforms for items (ii) and (iii). Here, we are plotting only the symbolic state, AU&0&0 (Au concatenated with 0 0, and the X. \D means decimal. Each waveform starts with the Initial (I) state and ends with the Initial state (I). clock_edge 0 clock_edge 1 clock_edge 2 clock_edge 3 clock_edge 4 clock_edge 5 clock_edge 6 clock_edge 7 clock_edge 8 clock_edge 9 clock_edge 10 clock_edge 11 clock_edge 12 clock_edge 13 clock_edge 14 clock_edge 15 SysClk Item (i) (Completed) STATE I CI CBUX DIV INC CBUX DIV FND I Au&0&0 12\D 16\D 20\D X 16\D 11\D 6\D 1\D -4\D ( 124\D ) 20\D 15\D 10\D 5\D 0\D STATE I CI CBUX Item (ii) Au&0&0 16\D X Item (iii) STATE I CI CBUX Au&0&0 28\D X EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

21 ee102_midterm2_sp2005.fm Host System Bu_Load Bu_in I0 Y I1 S Bu - Register Bu (B 6 B 5 B 4 B 3 B 2 ) SysClk 5 2 Bl_in N.C. Bin Ain 7 7 I Incrementer I+1 Au_in 5 (A_upper_in) Al_in (A_lower_in) I0 Y I1 S Au_Inc I0 Y I1 S Au_Load 0 0 Au - Register SysClk Au (A 6 A 5 A 4 A 3 A 2 ) Al_Load SysClk Al (A_Lower) DE CLK A 1 A 0 A 1 A 0 =/= 0 0 (A 1 A 0 isn t 0 0) Check A 1 A 0 Au Bu 5 5 X_MUX_S1 X_MUX_S0 X - 5 No-Connection 7 Xin I3 S1 I2 I1 I0 S0 Y X - Register 7 7 SysClk 7-bit number Found To perform a dummy load X <= X Comparator Au > Bu Au = Bu Au < Bu DataPath Unit ALREADY COMPLETE Subtractor 5 = X = Comparator X > 5 X = 5 X< 5 8 pts 2.3 Given below on the right-side is a portion of the above data-path. Show detailed design of this portion in the left-side box. Ain 0 D Q CLK A 0 A 1 A 0 =/= 0 0 Al_Load SysClk DE CLK Ain 1 Ain 0 Ain 1 D Q CLK A 1 A 1 A 0 Check A 1 A 0 Al_Load SysClk Elaborate this portion A 1 A 0 =/= 0 0 (A 1 A 0 isn t 0 0) 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

22 ee102_midterm2_sp2005.fm 2.4 Complete the state diagram below for the above design. I = Initial State CI = Compare A 1 A 0 with 0 0 and Increment Au if needed CBUX = Compare Au with Bu and Update X with Au&0&0 DIV = Divide by 5 by repetitively subtracting 5 INC = Increment Au by 1 FND = Found the number divisible by NSN = No Such Number All the states and the state transition arrows are in place. Complete the missing state transition conditions. Also fill-in RTL statements such as the following in appropriate states: 18 pts Au <= Au_in; Bu <= Bu_in; Al <= Al_in; Au <= Au + 1; X <= Au&0&0 (Au concatenated with two zeros); X <= X - 5; RESET START I CI CBUX START 1 1 DIV INC FND NSN ACK ACK ACK ACK 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

23 ee102_midterm2_sp2005.fm 8 pts 2.5 Complete NSL only for the two flip-flops Q DIV and Q CBUX below. You do not have to complete for the rest of the Flip-Flops (Q I, Q CI, Q INC, Q FND, Q NSN ). NSL NSL SysClk PRE Q D Q DIV CLK CLR SysClk PRE Q D CBUX Q CLK CLR 16 pts 2.6 Draw OFL to generate all outputs below. Complete the following table which helps in producing X_MUX_S1, X_MUX_S0. Portion of OFL to help generate X_MUX_S1, X_MUX_S0 Q CBUX Q DIV 1 0 State / RTL CBUX X <= Au&0&0 X_MUX X_MUX _S1 _S0 X_MUX_S Divide by 5 X <= X -5 Some other State Don t change X X_MUX_S1 Au_Load Au_Inc Al_Load Bu_Load 3 ( 6 points) 3 min. Sampling (capturing) (asynchronous / synchronous) inputs can cause a D-FF to go into metastability. The probability of conveying a metastable value to the rest of the design can be (reduced / increase) by adding a second level sample+hold flip-flop. The sample and hold flip-flop is always clocked by the (sender s clock / receiver s clock). 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

24 ee102_midterm2_sp2005.fm 4 ( 8 points) 5 min. Design a special down counter which counts down (7, 6, 5,...). However, it shall always skip 4. So the sequence shall be 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0,... Use the mux. to skip Subtracter A0 A1 A2 B0 B1 B2 S0 S1 S2 I00 I01 I02 I10 I11 I12 Mux Y0 Y1 Y2 S Register D D D Q Q Q SysClk LSB Q0 Q1 Q2 5 ( = 34 points) 30 min. 8 pts 5.1 Reproduced below is the state diagram for the divider from your classnotes. A student has modified state transition conditions on the two diverging arrows on the "C" state as shown. ~RESET START I (INITIAL) START X <== XIN; Y <== YIN; Q <== 0; X>=Y X>= Y C (COMPARE and UPDATE) If X >= Y X <== X - Y; Q <== Q + 1; X>= Y END Modified design Note Does it work? Yes / No START If it works, explain how it is better or worse in performance? If it does not work, state why it does not work. X > Y C (COMPARE and UPDATE) X > Y Note END D (DONE) Classnotes design 6 pts 5.2 In light of the above question, can you suggest an improvement to the Moore machine for the divider (reproduced from the classnotes below) by modifying the state transition conditions only? ~RESET START I (INITIAL) START X <== XIN; Y <== YIN; Q <== 0; X>=Y C (COMPARE) X>= Y 1 X>= Y END U (UPDATE) X <== X - Y; Q <== Q + 1; Explanation of improvement (if possible) or explanation why no improvement is possible: END D (DONE) Classnotes design 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

25 ee102_midterm2_sp2005.fm 8 pts Miss Trojan suggested a better Moore machine for the divider (better than the one in the classnotes and reproduced above) as shown below. Using the example 40 / 2 = 20, R=0, explain START "If" removed X > = Y why this is better than our classnotes design. ~RESET I (INITIAL) START X <== XIN; Y <== YIN; Q <== 0; C (COMPARE and UPDATE) X <== X - Y; Q <== Q + 1; U X > = Y (UNDO) X <== X + Y; Q <== Q - 1; END Note: "+" END D (DONE) 1 Note: "-" 6 pts Mr. Trojan says that there is still a little more to improve by playing with the state transition arrows and conditions! Can you guess what is in his mind by completing the design below? Using the example, 40 / 2 = 20, R=0, explain why START "If" removed this is little more better than Miss Trojan s design. ~RESET I (INITIAL) START X <== XIN; Y <== YIN; Q <== 0; C (COMPARE and UPDATE) X <== X - Y; Q <== Q + 1; END Note: "+" U (UNDO) X <== X + Y; Q <== Q - 1; END D (DONE) 1 Note: "-" 6 pts Mr. Trojan says that the resulting datapath of Miss Trojan s design or his design is a little more expensive. Please explain. 6 ( 6 points) 3 min. Whether a signal is 3.85V or 4.25V, a/an Clock (logic analyzer / oscilloscope) records it as a logic 1. Your lab partner said that the clock signal on the FPGA board has a lot of "ringing" (overshoot and undershoot). To identify this problem, he used a/an (logic analyzer/oscilloscope). If you want to measure the OFL (output function logic delay) using a logic analyzer, would you use it timing analyzer mode or state analyzer mode? timing analyzer mode / state analyzer mode 3/29/06 EE102L Midterm #2 - Spring / 10 C Copyright 2005 Gandhi Puvvada

EE201l Homework #8. Datapath Design

EE201l Homework #8. Datapath Design EE20l Homework #8 Datapath Design Instructor: G. Puvvada. Datapath and control design: You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the smaller in SMALL_REG and