University of Minnesota Department of Electrical and Computer Engineering
|
|
- Merry Freeman
- 5 years ago
- Views:
Transcription
1 University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID number. This eam is closed book and closed notes. Please remove all items from your desk other than pencils and eraser; this includes cell phones and calculators--no calculators or other electronic devices may be used during the eam. Show all of your work for a problem in the space provided on the eam sheet. If you need additional space, you must place a note with the problem indicating where the additional work is located. Answers without derivations are worth no credit. Please be sure that all parts of each problem have been completed. Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 Problem 8 Total (46 pts) (35 pts) (10 pts) (16 pts) (20 pts) (20 pts) (20 pts) (20 pts) (187 pts)
2 1(46) Circle the most correct answer, T (true) or F (false), to the following statements or do not answer. The scoring is +2 for a correct answer, 0 for no answer, and -2 for an incorrect answer. a) F Clock skew is the deterioration of the rise and fall times of clock signals as they propagate throughout a digital system. b) T A gate having an inertial delay of 10ns can be used to filter out glitches if their duration is less than 10ns. c) T Metastability in the flip-flops of a sequential circuit can occur if changes in the sequential circuit inputs are not synchronized with the clock signal. d) F A multiple level combinational circuit containing only NAND gates cannot contain static-0 hazards. e) T Tri-state buses allow bidirectional communication between devices. f) T Minimal implementations of two-level multiple output circuits may use nonminimal implementations of individual outputs. g) T There are 256 different combinational functions of 3 variables. h) T A sequential circuit always contains feedback. i) F A combinational circuit never contains feedback. j) F Unstable states in an asynchronous sequential circuit almost always cause oscillations in the circuit. k) F Hazards in combinational logic can be eliminated by properly adjusting the delays in the wires and gates of the circuit. l) T Equivalent states in a sequential circuit cannot be distinguished eperimentally by observing the response of the circuit to different input sequences. m) T Eliminating equivalent states in a state table permits its realization with a minimal number of flip-flops. n) T A sequential circuit consisting of a set of interconnected Mealy model circuits may have to operate at a slower clock speed than that of the slowest Mealy model circuit which it contains. o) F Hazards must be eliminated from the combinational logic in synchronous sequential circuits in order to obtain reliable operation. p) F The major disadvantage of one s complement representation of negative numbers over two s complement is the eistence of two zeros in one s complement. q) F If m i and M j are a minterm and a materm of n-variables, where i does not equal j, then m i + M j = m i. r) T If p i and p j are distinct prime implicants of a function f of n-variables, then p i + p j cannot be a prime implicant of f. s) F Two distinct essential prime implicants of a function f cannot cover (include) the same minterm. t) T The Boolean algebra identity w+(y+z)( +z) = (w+y+z)(w+ +z) illustrates the distributive property of Boolean algebra. u) F The Boolean algebra identity yz+ yz= yz illustrates the involution property of Boolean algebra. v) T The Boolean algebra identity wy+w z+ z+yz= wy+w z+ z can be verified using the distributive, DeMorgan and consensus properties of Boolean algebra. 2
3 2(35) The SM chart below describes a sequential circuit with two inputs, A and B and three outputs, X, Y and Z. (a) The circuit is to be implemented using four D FFs with outputs Q 4, Q 3, Q 2, and Q 1. The state assignment is State Q 4 Q 3 Q 2 Q 1 S S S S S Derive FF ecitation equations and output equations. You need not draw the circuit. (b) Using the guidelines discussed in class and the tet for finding a good state assignment for sequential circuits, find a good minimal state assignment for this circuit. You can ignore the outputs and you need not give the equations, just give the state assignment. Assign all 0 s to S 0. 3
4 (a) D 1 = AQ 4 Q 3 Q 2 Q 1 + Q 4 = AQ 3 Q 2 Q 1 + Q 4 + A B Q 1 D 2 = A BQ 1 D 3 = AQ 1 D 4 = Q 3 X = Q 4 Q 3 Q 2 Q 1 + Q 3 Y = AQ 4 Q 3 Q 2 Q 1 + A BQ 1 Z = AQ 1 + A BQ 1 b. AB S0 S0 S0 S1 S1 S1 S0 S2 S3 S3 S2 S3 S2 S2 S3 S3 S4 S4 S4 S4 S4 S0 S0 S0 S0 H1: (S0,S1), (S0,S4), (S1,S4) (S0,S4), (S1,S2) (S1,S2) =(S0,S1), (S0,S4) 2, (S1,S4), (S1,S2) 2 H2: (S0,S1) 4 (S0,S2), (S0,S3) 2 (S2,S3) 4 Two possible assignments: S0 = 000 S1 = 100 S2 = 110 S3 = 010 S4 = 001 and S0 = 000 S1 = 100 S2 = 101 S3 = 001 S4 = 010 4
5 3(10) Realize an SR latch with just two components: 1) a 3-to-8 decoder with active high outputs, no enable and 2) a NOR gate with up to 8 inputs. The inputs to the NOR are the minterms of Q, S and R for which Q + is a 0. (Thinking of a NOR as an OR followed by an inverter, the output of the OR should be the complement of the function at the output of the NOR; hence, the minterms of the complement function should be ORed.) If Q, S and R are the I 2, I 1, and I 0 inputs to decoder, then Y 0, Y 1, and Y 5 from the decoder are the inputs to the NOR gate. 4(16) A positive edge-triggered, LM flip-flop operates as shown in the transition table below. L M CP Q Q LM flip-flops are to be used to implement the following transition table. Construct the ecitation table for the B FF. (You don t need the ecitation table for the A FF. AB ,-1 0-, ,1- -0,1- LA,MA AB , , , LB,MB AB
6 5(20) Construct a Mealy state diagram, with a minimum number of states, for a sequential circuit with two inputs, and y, and one output, z. At each clock time, the most-recent two inputs on is considered to be a 2-bit unsigned, binary number; similarly, the mostrecent two inputs on y is considered to be a 2-bit unsigned, binary number. (For both and y, the most recent input is the least significant bit of the two-bit number.) z is 1 if the sum of these two 2-bit numbers is divisible by 3; otherwise, z is 0. (Note: 0 is divisible by 3.) For the first and y input combination, the circuit responds as if the previous and y input combination had been 00. An eample input/output sequence is : y: z: Mealy Circuit Past Present y sum State , 1 2, 0 3, 0 2, , 0 2, 1 3, 0 2, , 0 2, 0 3, 1 2, 0 6(20) A certain EE2301 student claims that the two circuits below implement the same combinational logic function. Prove or disprove her claim. Show your derivation. Circuit on left (A + C)(B E + C ) + CDF = A B E + A C + B CE + CDF = A C + B CE + CDF (consensus of A C and B CE) Circuit on right (A + C)(B E + C + D F ) = A B E + A C + A DF + B CE + CDF = A B E + A C + B CE + CDF (consensus of A C and CDF ) = A C + B CE + CDF (consensus of A C and B CE). The two circuits implement the same function. 6
7 7(20) Find the minimal row state table that is equivalent to the one below. Show your derivation. 1 2 S ,0 5,1 4,1 1,0 2 1,1 8,0 3,1 5,1 3 6,0 5,1 4,1 1,0 4 2,0 5,1 3,1 4,0 5 2,1 5,1 3,0 7,0 6 3,1 8,0 1,1 5,1 7 1,1 6,0 4,1 5,1 8 4,1 2,0 1,1 4,1 Equivalent States: 134,26,5,7,8 1 2 S ,0 5,1 1,1 1,0 2 1,1 8,0 1,1 5,1 5 2,1 5,1 1,0 7,0 7 1,1 2,0 1,1 5,1 8 1,1 2,0 1,1 1,1 7
8 8(20) The state table below is to be implemented using a minimum number of JK flip-flops and a minimal number of gates (AND, OR and inverters). State A is the initial state and has a state assignment of all 0 s. Derive the FF ecitation equations and the output equation. 0 1 Z A B A 0 B B C 0 C C C 1 Using the state assignment A = 00, B = 01, and C = 11, the transition and output tables become 0 1 Z For JK flip-flops, the ecitation and output tables are q1q0 0 1 Z , 1-0 -, , , , - 0-0, , , J1 = q0, K1 = 0, J2 =, K2 = 0, Z = q1 Using the state assignment A = 00, B = 01, and C = 10, the transition and output tables become 0 1 Z For JK flip-flops, the ecitation and output tables are q1q0 0 1 Z , 1-0 -, , , , , , , J1 = q0, K1 = 0, J2 = q1, K2 =, Z = q1 8
Synchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationProblem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
More informationChapter 9 Asynchronous Sequential Logic
9.1 Introduction EEA051 - Digital Logic 數位邏輯 Chapter 9 Asynchronous Sequential Logic 吳俊興高雄大學資訊工程學系 December 2004 Two major types of sequential circuits: depending on timing of their signals Asynchronous
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationCPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic
CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationEECS 270 Midterm 2 Exam Answer Key Winter 2017
EES 270 Midterm 2 Exam nswer Key Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This part of the exam
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationBER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO
UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a
More informationXI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.
2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two
More informationSequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More information15.1 Elimination of Redundant States
15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationEE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationvidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More information11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of
EE 2449 Experiment 11 Jack Levine and Nancy Warter-Perez CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 11 SEQUENTIAL CIRCUITS
More informationENEL Digital Circuit Design. Final Examination
ELECTRICAL AND COMPUTER ENGINEERING ENEL 353 - Digital Circuit Design Final Examination Friday, December 17, 1999 Red Gymnasium, 3:30PM - 6:30 PM Instructions: Time allowed is 3 hours. The examination
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationReview for B33DV2-Digital Design. Digital Design
Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation
More informationTime Allowed 3:00 hrs. April, pages
IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using
More informationENEL Digital Circuits Final Examination
Name: I#: Lecture Section: ENEL 353 - igital Circuits Final Examination Lecture sections : N. R. Bartley, MWF : :5, ENC 24 2: S. A. Norman, MWF : :5, ST 45 Wednesday, ecember 7, 24 Time: 7: PM : PM Locations:
More informationDigital Electronics Final Examination. Part A
Digital Electronics Final Examination Part A Spring 2009 Student Name: Date: Class Period: Total Points: /50 Converted Score: /40 Page 1 of 13 Directions: This is a CLOSED BOOK/CLOSED NOTES exam. Select
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationDigital Logic Design - Chapter 4
Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationChapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
More informationLecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, Second Semester: 2015/2016 Dept. of Computer Engineering Course Title: Logic Circuits Date: 08/06/2016
More informationSequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
More informationII. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):
ENGI 386 Digital Logic II. COMBINATIONAL LOGIC DESIGN Combinational Logic output of digital system is only dependent on current inputs (i.e., no memory) (a) Boolean Algebra - developed by George Boole
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationFaculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY
1 McGill University Faculty of Engineering DIGITAL SYSTEM DESIGN ECSE-323 FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Signature: Associate
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationSchedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.
Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon
More informationWritten exam with solutions IE1204/5 Digital Design Friday 13/
Written eam with solutions IE204/5 Digital Design Friday / 207 08.00-2.00 General Information Eaminer: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani
More informationCHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationWritten exam for IE1204/5 Digital Design with solutions Thursday 29/
Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when
More informationCSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008
CSE 14 Midterm 2 Tajana Simunic Rosing Spring 28 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages.
More informationEE 209 Spiral 1 Exam Solutions Name:
EE 29 Spiral Exam Solutions Name:.) Answer the following questions as True or False a.) A 4-to- multiplexer requires at least 4 select lines: true / false b.) An 8-to- mux and no other logic can be used
More informationChapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 JK Flip-Flop ve edge triggered Output Q and
More informationEET 310 Flip-Flops 11/17/2011 1
EET 310 Flip-Flops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not
More informationCS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman
CS 121 Digital Logic Design Chapter 2 Teacher Assistant Hanin Abdulrahman 1 2 Outline 2.2 Basic Definitions 2.3 Axiomatic Definition of Boolean Algebra. 2.4 Basic Theorems and Properties 2.5 Boolean Functions
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationCh 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1
Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:
More informationCh 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1
Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential
More informationContents. Chapter 3 Combinational Circuits Page 1 of 36
Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of
More informationDigital electronics form a class of circuitry where the ability of the electronics to process data is the primary focus.
Chapter 2 Digital Electronics Objectives 1. Understand the operation of basic digital electronic devices. 2. Understand how to describe circuits which can process digital data. 3. Understand how to design
More informationUnit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4
Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary
More informationCOMPUTER SCIENCE TRIPOS
CST0.2017.2.1 COMPUTER SCIENCE TRIPOS Part IA Thursday 8 June 2017 1.30 to 4.30 COMPUTER SCIENCE Paper 2 Answer one question from each of Sections A, B and C, and two questions from Section D. Submit the
More informationCombinational Logic Design Principles
Combinational Logic Design Principles Switching algebra Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Switching algebra Axioms of switching algebra Theorems
More informationFundamentals of Boolean Algebra
UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and
More informationFinal Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90
Final Exam ECE 25, Spring 2008 Thursday, June 12, 2008 Name: PID: Problem Points Score 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 Total 90 1) Number representation (10 pts) a) For each binary vector
More informationWritten reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
More informationDO NOT COPY DO NOT COPY
Drill Problems 3 benches. Another practical book is VHDL for Programmable Logic, by Kevin Skahill of Cypress Semiconductor (Addison-esley, 1996). All of the ABEL and VHDL examples in this chapter and throughout
More informationComputer Science Final Examination Friday December 14 th 2001
Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,
More informationBoolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation
More informationUniversity of Florida EEL 3701 Fall 2014 Dr. Eric. M. Schwartz Department of Electrical & Computer Engineering Wednesday, 15 October 2014
Page 1/12 Exam 1 May the Schwartz Instructions: be with you! Turn off all cell phones and other noise making devices and put away all electronics Show all work on the front of the test papers Box each
More informationUNIVERSITI TENAGA NASIONAL. College of Information Technology
UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationPractice Final Exam Solutions
The University of Michigan Department of Electrical Engineering and Computer Science EECS 270 Fall 2003 Practice Final Exam Solutions Name: UM ID: For all questions, show all work that leads to your answer.
More informationDigital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..
Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationEECS 270 Midterm Exam 2 Fall 2009
EECS 270 Midterm Exam 2 Fall 2009 Name: unique name: UMID: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1&2
More informationECE20B Final Exam, 200 Point Exam Closed Book, Closed Notes, Calculators Not Allowed June 12th, Name
C20B Final xam, 200 Point xam Closed Book, Closed Notes, Calculators Not llowed June 2th, 2003 Name Guidelines: Please remember to write your name on your bluebook, and when finished, to staple your solutions
More informationAppendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
More informationLogic Gate Level. Part 2
Logic Gate Level Part 2 Constructing Boolean expression from First method: write nonparenthesized OR of ANDs Each AND is a 1 in the result column of the truth table Works best for table with relatively
More informationMemory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1
Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember
More informationIntroduction to Digital Logic
Introduction to Digital Logic Lecture 17: Latches Flip-Flops Problem w/ Bistables Output should have been at end of sequence Problem: Glitch was remembered Need some way to ignore inputs until they are
More informationSynchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER
Synchronous Sequential Logic Part I BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Sequential Logic Digital circuits we have learned, so far, have been combinational no memory,
More informationBoolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra
Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming
More informationKUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : S_CS_C_Digital Logic_588 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: -56 CLASS TEST 8-9 COMPUTER SCIENCE & IT Subject : Digital
More informationChapter 7 Sequential Logic
Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics
More informationDigital Circuits and Systems
EE201: Digital Circuits and Systems 4 Sequential Circuits page 1 of 11 EE201: Digital Circuits and Systems Section 4 Sequential Circuits 4.1 Overview of Sequential Circuits: Definition The circuit whose
More informationLecture 9: Digital Electronics
Introduction: We can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit parameter of interest: nalog: The voltage can
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University
More information