課程名稱 : 數位邏輯設計 P-1/ /6/11

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1 課程名稱 : 數位邏輯設計 P-1/ /6/11 Textbook: Digital Design, 4 th. Edition M. Morris Mano and Michael D. Ciletti Prentice-Hall, Inc. 教師 : 蘇慶龍 INSTRUCTOR : CHING-LUNG SU kevinsu@yuntech.edu.tw

2 Chapter 8 P-2/ /6/11 Chapter 8 Design at the Register Transfer Level

3 Outline of Chapter 8 P-3/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

4 8.1 Introduction P-4/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

5 8.1 Introduction P-5/ /6/11 A digital system is a sequential logic system constructed with flip-flops and gates. 1. To specify a large digital system with a state table is very difficult. 2. Modular subsystems 3. Registers, decoders, multiplexers, arithmetic elements and control logic 4. They are interconnected with datapaths and control signals.

6 8.2 Register Transfer Level Notation P-6/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.8 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

8.2 Register Transfer Level Notation P-7/55 2012/6/11 RTL 1.

7 8.2 Register Transfer Level Notation P-7/ /6/11 RTL 1. Register Transfer Level (RTL): The information flow and processing perform on the data stored in the registers is referred to as register transfer operations. 2. A large digital system is presented at the register transfer level when it is specified by the following three components: 1: The set of registers in the system 2: The operations that are performed on the data stored in the registers 3: The control that supervises the sequence of operations in the system

8 Register MUX Register Register Register 8.2 Register Transfer Level Notation P-8/ /6/11 Controller RTL (Continued) RTL 1 IF Combination Logic Gates Combination Logic Gates Combination Logic Gates Combination Logic Gates RTL 2 RTL 3

9 8.2 Register Transfer Level Notation P-9/ /6/11 R2 RTL Notations R1 : Contents of R1 transfer into R2 IF (T1=1) then (R2 R1) Concurrently IF (T3=1) then (R2 R1, R1 R2) : Exchange R1, R2 R1 R3 R4 R1+R2 : Add Content of R2 to R1 R3+1 : Increase R3 by 1 (Count up) shr R4 : Shift right R4 R5 0 : Clear R5 to 0

10 8.2 Register Transfer Level Notation P-10/ /6/11 Four Types of Operations in a Digital System 1. Transfer operations that transfer data from one register to another. 2. Arithmetic operations that perform arithmetic on data in registers. 3. Logic operations that perform bits manipulation of non-numeric data in registers. 4. Shift operations that shift data in registers

11 8.3 Register Transfer Level in HDL P-11/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

12 8.3 Register Transfer Level in HDL P-12/ /6/11 HDL Programming referred to TA

13 8.3 Register Transfer Level in HDL P-13/ /6/11 Process of HDL Simulation and Synthesis HDL Description of Design Valid Design Synthesis Tools Synthesis Gate-level Netlist Simulation RTL Design Test Bench Simulation Gate-level Design Needs Corerection Results OK! OK! Results Needs Corerection No Match Comparison Match! Fabricate IC

14 8.4 Arithmetic State Machines (ASMs) P-14/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

15 8.4 Arithmetic State Machines (ASMs) P-15/ /6/11 Control and Datapath Interaction Status Conditions Inputs Control Logic (Controller) Commands (Control Signals) Inputs Datapath (Data Compuating) Outputs Adders Decoder Multiplexer Counter Shift Register

16 8.4 Arithmetic State Machines (ASMs) P-16/ /6/11 Algorithmic State Machine (ASM) 1. Algorithmic State Machine (ASM): A special flow chart that has been developed specifically to define digital hardware algorithm. 2. State Machine: A term for a sequential circuit. 3. ASM Chart: The ASM chart describes the sequence of events as well as the timing relation ship between the states of sequential controller and the events that occur while going from one state to the next.

17 8.4 Arithmetic State Machines (ASMs) P-17/ /6/11 ASM Chart: State Box + Decision Box + Conditional Box State Box: Name Binary Code T Register Operation or Output R 0 START (a) General Description (b) Specific Example Decision Box: 0 1 Condition Exit Path Exit Path

18 8.4 Arithmetic State Machines (ASMs) P-18/ /6/11 Conditional Box and a Example Example with Conditional Box: T General Description: START From exit path of decision box Register Operation or Output 0 E 1 R 0 T F E

19 8.4 Arithmetic State Machines (ASMs) P-19/ /6/11 ASM Block : 1 Clock Period (RTL) T ASM Block A A+1 0 E 1 State Diagram Equivalent to ASM Chart 001 EF=00 E=1 0 1 F R EF= T T T

20 8.4 Arithmetic State Machines (ASMs) P-20/ /6/11 Timing Considerations Clock Present State (T 1 ) Next State (T 2 or T 3 or T 4 ) 1. Register A is increased 2. If E=1, then register R is cleared 3. Control transfer to the next state as specified in previous slice.

21 8.5 Design Example P-21/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

22 8.5 Design Example P-22/ /6/11 Design Descriptions 1. System with 2 FFs (E and F), a 4-bit binary counter A (A 4 A 3 A 2 A 1 ) 2. A 4 : Most Signification Bit (MSB) 3. In initiation signal S clear A and F 4. Counter is increased by clock pulse 5. If A 3 =0, E is cleared to 0 and the counter continues 6. If A 3 =1, E is set to 1; then if A 4 =0, the count continues, but if A 4 =1, F is set to 1 on next clock pulse and the system stops counting 7. Then if S=0, the system remains in the initial state, but if S=1, the operation cycle repeats.

23 8.5 Design Example P-23/ /6/11 T 0 00 Initial State 0 S T 0 ASM Block ASM Chart for Design Example T 1 1 A 0 F 0 A A+1 T 1 A 3 =0 G 1 G 0 =01 A 3 A 4 =10 T A 3 E 0 E 1 A 4 0 T 2 1 A 3 A 4 =11 11 F 1

24 Delay 1 Cycle 8.5 Design Example P-24/ /6/11 Timing Sequence: Response Delay 1 Cycle Operation Sequence Counter Flip-Flop A 4 A 3 A 2 A 1 E F Condition State Delay 1 Cycle A 3 =0, A 4 =0 T A 3 =1, A 4 = A 3 =0, A 4 = A 3 =1, A 4 = T T 0 Delay 1 Cycle

25 8.5 Design Example P-25/ /6/11 Datapath Design Start S T 0 T 0 =1,S=1 A 4 Controller T 1 T 1 =1,E=A 3 A 3 Clock T 2 J C K E T 2 =1 J C K F A 4 A 3 A 2 A 1 4-Bit Counter with Synchronous Clear Count Clear T 0 =1,S=1 Clock

26 8.5 Design Example P-26/ /6/11 Register Transfer Representation S=0 A 3 =0 Register Transfer Operations T 0 : if (S=1) then A 0, F 0 T 0 S=1 T 1 T A 2 3 A 4 =11 T 1 : A A+1 if (A 3 =1) then E 1 if (A 3 =0) then E 0 A 3 A 4 =10 T 2 : F 1 State Diagram

27 8.5 Design Example P-27/ /6/11 State Table State Table for Controller Present Next Present-State State Inputs State Outputs Symbol G 1 G 0 S A 3 A 4 G 1 G 0 T 0 T 1 T 2 T X X T X X T X 0 X T X T X T X X X T 0 =G 0 T 2 =G 1

28 8.5 Design Example P-28/ /6/11 Control Logic (Controller) Design S D G 0 D G1 = T 1 A 3 A 4 D G0 = T 0 S+T 1 T 0 = G 0 T 1 = G 1 G 0 T 2 = G 1 A 3 A 4 C D G 1 Clear T 0 T 2 C T 1 Clock Clear

29 8.6 HDL Description of Design Example P-29/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

30 8.6 HDL Description of Design Example P-30/ /6/11 Referred to TA

31 8.7 Sequential Binary Multiplier P-31/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

32 8.7 Sequential Binary Multiplier P-32/ /6/11 Example for Binary Multiplications Multiplicand (n-bit) Multiplier (m-bit) Product (n+m Bits)

33 8.7 Sequential Binary Multiplier P-33/ /6/11 Register Configuration Check for Zero Z=1 if P=0 Z Control Logic P Counter (Down Counter) S (Start) Register B Multiplicand Initial Value = n (Bit Number of Multiplier) CAQ C out Parallel Adder Sum Initial Value = 0 C Register A Initial Value=0 Register Q Multiplier Q 0 Product

8.7 Sequential Binary Multiplier P-34/55 2012/6/11 T 0 Initial State T 1 0 S 1 A 0 C 0 P n ASM Chart T 2 P P-1

34 8.7 Sequential Binary Multiplier P-34/ /6/11 T 0 Initial State T 1 0 S 1 A 0 C 0 P n ASM Chart T 2 P P Q 0 A A+B, C C out Shift CAQ, C 0 A shr A, A n-1 C, Q shr Q, Q n-1 A 0, C 0 T 3 Shift Right CAQ, C Z

35 8.7 Sequential Binary Multiplier P-35/ /6/11 Numerical Example for Binary Multiplier Multiplicand B=10111 C A Q P Multiplier in Q Q 0 =1; add B First partial product Shift right CAQ Q 0 =1; add B Second partial product Shift right CAQ Q 0 =0; shift right CAQ Q 0 =0; shift right CAQ Q 0 =1; add B Fifth partial product Shift right CAQ Final Product in CAQ =

36 8.8 Control Logic P-36/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

37 8.8 Control Logic P-37/ /6/11 Control Specifications for Binary Multiplier Register Transfer Operations T 0 : Initial State T 1 : A 0, C 0, P n T 2 : P P-1 if (Q 0 )=1 then (A A+B, C C out ) T 3 : Shift Right CAQ, C 0 State Diagram S=0 Z=1 T 0 T 1 T 2 T 3 S=1 Z=0

38 8.8 Control Logic P-38/ /6/11 Control Block Diagram and State Assignment Control Block Diagram Z S Q 0 Control Logic T 0 T 1 T 2 T 3 L=Q 0 T 2 Addition State Assignment for Control State Binary Gray Code One-Hot T T T T

39 8.8 Control Logic P-39/ /6/11 Sequence Register and Decoder State Table for Control Circuit Present Next State Input State Outputs G 1 G 0 S Z G 1 G 0 T 0 T 1 T 2 T X X X X X X X X T 3 Z Next State: D G1 = T 1 + T 2 + T 3 Z D G0 = T 0 S + T 2

40 8.8 Control Logic P-40/ /6/11 Control Logic Diagram of a Binary Multiplier S D C G X4 Decoder T 0 T 1 T 2 T 3 Z D G 1 C Q 0 L=T 2 Q 0 Clock

41 8.8 Control Logic P-41/ /6/11 One Flip-Flop per State (One-Hot) without Decoder State Table for One-Hot Controller T 0 S T 3 Z Present Next State Input State Outputs S Z T 0 T 1 T 2 T 3 T 0 0 X T T 0 1 X T T 1 X X T T 2 X X T T 3 X 0 T T 3 X 1 T Next State: D T0 = T 0 S + T 3 Z D T1 = T 0 S D T2 = T 1 + T 3 Z D T3 = T 2

42 8.8 Control Logic P-42/ /6/11 S Z T 0 S +T 3 Z D C T 0 One Flip-Flop per State (One-Hot) Controller D C D C T 1 T 2 D T 3 C Clock

43 8.9 HDL Description of Binary Multiplier P-43/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

44 8.9 HDL Description of Binary Multiplier P-44/ /6/11 Referred to TA

45 8.10 Design With Multiplexers P-45/ /6/ Introduction 8.2 Register Transfer Level (RTL) Notation 8.3 Register Transfer Level in HDL 8.4 Algorithmic State Machines (ASMs) 8.5 Design Example 8.6 HDL Description of Design Example 8.7 Sequential Binary Multiplier 8.8 Control Logic 8.9 HDL Description of Binary Multiplier 8.10 Design With Multiplexers

46 8.10 Design With Multiplexers P-46/ /6/11 3-Level Controller Implementations with Multiplexers 1 st. Level: Multiplexers determines the next state of the register. 2 nd. Level: Registers hold the present binary state. 3 rd. Level: Decoders provide a separate output for each control state.

47 8.10 Design With Multiplexers P-47/ /6/11 T 0 00 w 0w 1w T 1 01 Design Example x 0 x 1 x T 3 11 T z 0 y 1 1 y 0 yz 1 1 z 0 yz y

48 8.10 Design With Multiplexers P-48/ /6/11 Control Implementation with Multiplexers y z y z 0 1 y w x y MUX 1 S 1 S 0 S 1 S 0 MUX 2 D C D C G 1 G 0 2X4 Decoder T 0 T 1 T 2 T 3 Clock

49 8.10 Design With Multiplexers P-49/ /6/11 Multiplexer Input Conditions Multiplexer Input Conditions Present Next State State Input Inputs G 1 G 0 G 1 G 0 Conditions MUX1 MUX w w 0 w x x 1 x y yz yz +yz=y yz yz y z y y+y z =y+z y z+y z =y y z

50 8.10 Design With Multiplexers P-50/ /6/11 Design Example: Count the Number of Ones in a Register 1. The system to be designed consists of two registers, R1 and R2, and a flip-flop E. 2. The system counts the number of 1 s in the number loaded into R1 and sets register R2 to that number. Example: R1 = R2 = 101 Solution: 1. Shift each bit from R1 one at a time into flip-flop E 2. If E=1, then R2 is increased by 1 3. If R1=0, then Z=1

51 Complete 8.10 Design With Multiplexers P-51/ /6/11 T 0 00 Initial State 0 R1 R2 S 1 Input All 1's ASM Chart for Countof-Ones Circuit T 1 01 R2 R2+1 Z 1 0 T 2 10 Shift R1 to E T 3 11 E 1 0

8.10 Design With Multiplexers P-52/55 2012/6/11 Start S E Z Control T 0 T 1 T 2 T 3 Z=1 if R1=0 Block Diagram for Count-of-Ones E D Check for Zero

52 8.10 Design With Multiplexers P-52/ /6/11 Start S E Z Control T 0 T 1 T 2 T 3 Z=1 if R1=0 Block Diagram for Count-of-Ones E D Check for Zero Parallel Output Shift Register R1 Serial Input=0 Shift Left Load Input C Input Data Clock Output Count Counter R2 Count Load Input Input = All 1's

53 8.10 Design With Multiplexers P-53/ /6/11 Multiplexer Input Conditions for Design Example Present Next Multiplexer State State Input Inputs G 1 G 0 G 1 G 0 Conditions MUX1 MUX S S 0 S Z Z Z None E E E E

8.10 Design With Multiplexers P-54/55 2012/6/11 0 Z 1 E S 0 1 E Control Implementation for

54 8.10 Design With Multiplexers P-54/ /6/11 0 Z 1 E S 0 1 E Control Implementation for Count-of-One Circuit MUX 1 S 1 S 0 S 1 S 0 MUX 2 Clock D C D C G 1 G 0 2X4 Decoder T 0 T 1 T 2 T 3

55 P-55/ /6/11 Have a nice summer vacation!

Design at the Register Transfer Level

Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic