CSE140: Digital Logic Design Registers and Counters

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1 CSE14: Digital Logic Design Registers and Counters Prof. Tajana Simunic Rosing 38

2 Where we are now. What we covered last time: ALUs, SR Latch Latches and FlipFlops (FFs) Registers What we ll do next FSMs Upcoming deadlines: ZyBook today: Sec 5.1-6, Thursday: Sec HW#4 due today, HW#5 due next Tuesday Quiz #5 Thursday Midterm #2 coming up next week Discussion session next Monday will help prepare for midterm Textbook references: chap 3, Sec 6.3 Prof. office hours this week: Tuesday 5-6pm Thursday 1:3-2:3pm (instead of starting at 2:2pm) TA/Tutor office hours back to full schedule starting Thursday

3 Design of a Universal Shift Register left_in left_out clear s s1 output input right_out right_in clock clear s s1 new value 1 output 1 output value of FF to left (shift right) 1 output value of FF to right (shift left) 1 1 input Nth cell to N-1th cell Q D to N+1th cell CLEAR s and s1 control mux Q[N-1] (left) Input[N] Q[N+1] (right)

4 Counters Sequences through a fixed set of patterns OUT1 OUT2 OUT3 OUT4 IN D Q D Q D Q D Q 41

5 General Counters Default operation: count up QA-QD counter output A-D parallel load data LOAD enables data load RCO ripple carry out CLR clears data EN counter enable "1" "" "1" "1" "" "" EN RCO D QD C QC B QB A QA LOAD CLR "1" "" "" "" "" EN RCO D QD C QC B QB A QA LOAD CLR 42

6 Finite State Machines 43

7 Circuit Specifications Combinational Logic Truth tables, Boolean equations, logic diagrams (no feedback) Sequential Networks: State Diagram (Memory) State and Excitation Tables Characteristic Expression Logic Diagram (FFs and feedback loops) Y A B C D Combinational X RTL: Register-Transfer Level Description 44

8 Finite State Machines: Two Bit Counter Example Symbol/ Circuit Current state Next State 2 bit Counter S S 1 S 1 S 2 S 2 S 3 S 3 S S Q 1 (t) Q (t) Q 1 (t+1) Q (t+1) S 3 S 1 S 2 State Diagram State Table

9 Which is the most likely circuit realization of the two bit counter? State Table Q 1 (t) Q (t) Q 1 (t+1) Q (t+1) A. Combinational circuit Circuit with no flip flops B. C. Q (t) Combinational circuit Q 1 (t) D Q Q D Q Q Q (t) Q 1 (t) Combinational circuit D Q Q Circuit with 2 flip flops Circuit with one flip flop

10 Two Bit Counter Circuit State Table Q 1 (t) Q (t) Q 1 (t+1) Q (t+1) Q D Q (t) Q Q D Q Q 1 (t) We store the current state using D-flip flops so that: Inputs to the combinational circuit don t change while the next output is computed The transition to the next state only occurs at the rising edge of the clock D (t) = Q (t) D 1 (t) = Q (t) Q 1 (t) + Q (t) Q 1 (t) Implementation of 2-bit counter

11 FSM Definition FSM consists of Set of states Set of inputs, set of outputs I a b A B Initial state Set of transitions Only one can be true at a time FSM representations: State diagram State table 48

12 FSM Example Wait u= s s ar ab ag ar Inputs: s,r,g,b,a; Outputs: u Is this FSM fully defined? A. Yes B. No Start a u= ar Red1 u= ab Blue ag Green ar Red2 a u= a u= a u=1 u= s Wait s Watch for transition properties! (note that more transitions need to be added) Start u= ar Red1 u= a ab ag ar Blue Green Red2 a a a u= u= u=1

13 FSM Controller Design Process with a Three Bit Counter Example 1. State Diagram 2. State Table 3. State Assignments Excitation Table (present state, inputs; next state, outputs) 5. Circuit State Table with Assigned State Patterns C3 C2 C1 N3 N2 N "1" bit up-counter FSM 11 Circuit DQ DQ DQ 1 OUT1 OUT2 OUT3 5

14 Mealy and Moore Machines Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) x(t) C1 C2 y(t) x(t) C1 C2 y(t) Mealy Machine S(t) Moore Machine S(t)

15 A. Moore machine B. Mealy machine C. None of the above This Counter Design Is: OUT1 OUT2 OUT3 D Q D Q D Q "1"

16 Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 1 from its life detection sensors, it means that the it has detected life on Mars and the output y(t) = 1, otherwise y(t) = (no life on Mars ). This pattern recognizer should have A.One state because it has one output B.One state because it has one input C.Two states because the input can be or 1 D.More than two states because. E.None of the above 53

17 Mars Life Recognizer FSM Which of the following diagrams is a correct Mealy solution for the 1 pattern recognizer on the Mars rover? 1/1 A. 1/ S / S1 / S2 / 1/ B. 1/ / S / S1 1/1 S2 1/ C. Both A and B are correct / D. None of the above 54

18 Pattern Recognizer 1 1/ S / 1/ Mars Life Recognizer FFs 1/1 S1 / S2 / x(t) C1 Mealy Machine What does state table need to show to design controls of C1? A.(current input x(t), current state S(t) vs. next state, S(t+1)) B.(current input, current state vs. current output y(t)) C.(current input, current state vs. current output, next state) D.None of the above C2 S(t) 55 y(t)

19 State Diagram => State Table with State Assignment 1/1 x(t) 1/ S / 1/ S1 / S2 / C1 C2 S(t) Mealy Machine y(t) S(t)\x 1 S S1, S, S1 S2, S, S2 S2, S,1 State Assignment S: S1: 1 S2: 1 S(t)\x 1 1,, 1 1,, 1 1,,1 Q 1 (t+1)q (t+1), y 56

20 State Diagram => State Table => Excitation Table => Circuit Q 1 (t) Q (t)\x 1 1,, 1 1,, 1 1,,1 x(t) C1 C2 S(t) Mealy Machine y(t) id Q 1 Q x D 1 D y X X X X X X 57

21 State Diagram => State Table => Excitation Table => Circuit id Q 1 Q x D 1 D y X X X X X X D1(t): x(t) Q X X D1(t) = x Q + x Q1 D (t)= Q 1Q x y= Q 1 x Q 1 58

22 State Diagram => State Table => Excitation Table => Circuit Q 1 Q x x Q D D1 D D Q Q Q Q Q Q1 y Q1 x x(t) D1(t) = x Q + x Q1 D (t)= Q 1Q x y= Q 1 x C1 C2 S(t) Mealy Machine y(t) 59

23 Moore FSM for the Mars Life Recognizer Which of the following diagrams is a correct Moore solution to the 1 pattern recognizer? 1/1 A. 1/ S / S1 / S2 / B. 1 S 1/ S1,1 S2 1 S3 1 1 C. Both A and B are correct D. None of the above 6

24 Moore Mars Life Recognizer: FF Input Specs Pattern Recognizer 1 1 S S1,1 S2 1 S3 1 x(t) C1 C2 S(t) y(t) 1 Moore Machine What does state table need to show to design controls of C2? A.(current input x(t), current state S(t) vs. next state, S(t+1)) B.(current input, current state vs. current output y(t)) C.(current state vs. current output y(t) and next state) D.(current state vs. current output y(t) ) E.None of the above 61

25 1 S Moore Mars Life Recognizer: State Table,1 S1 1 S(t)\x 1 S S1, S, S1 S2, S, S2 S2, S3, S3 S,1 S,1 Q 1 Q \x 1 1,, 1 1,, 1 1, 11, 11,1,1 Q 1 (t+1)q (t+1), y S2 1 S3 1 ID Q 1 Q x D 1 D y

26 Mars Life Recognizer: Combinational Circuit Design id Q 1 Q x D 1 D y D1(t): D(t): y(t): x(t) x(t) x(t) Q Q 1 Q Q 1 Q Q Sources: TSR, Katz, 1 Boriello & Vahid

27 Mars Life Recognizer Circuit Implementation State Diagram => State Table => Excitation Table => Circuit D D1 D D Q Q Q Q Q Q1 y x(t) C1 C2 y(t) S(t) Moore Machine 64

ALU, Latches and Flip-Flops

CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades