State and Finite State Machines

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1 State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University

2 Big Picture: Building a Processor memory inst register file alu PC new pc offset target imm control extend =? cmp addr d in d out memory A Single cycle processor

3 Review: Efficiency and Generality We can generalize 1 bit Full Adders to 32 bits, 64 bits A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 C 0 S 3 S 2 S 1 S 0

4 Review: Efficiency and Generality We can generalize 1 bit Full Adders to 32 bits, 64 bits How long does it take to compute a result? Can we store the result? B 3 B 2 B 1 B 0 over flow A 3 mux mux mux A 2 A 1 A mux 0 0=add 1=sub S 3 S 2 S 1 S 0

5 Performance Speed of a circuit is affected by the number of gates in series (on the critical path or the deepest level of logic) inputs arrive Combinational Logic outputs expected t combinational

6 4 bit Ripple Carry Adder A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 C 4 C 3 C 2 C 1 C 0 S 3 S 2 S 1 Carry ripples from lsb to msb S 0 First full adder, 2 gate delay Second full adder, 2 gate delay

7 Stateful Components Until now is combinatorial logic Output is computed when inputs are present System has no internal state Nothing computed in the present can depend on what happened in the past! Inputs N Combinational circuit M Outputs Need a way to record data Need a way to build stateful circuits Need a state holding device Finite State Machines

8 Goals for Today State How do we store one bit? Attempts at storing (and changing) one bit Set Reset Latch D Latch D Flip Flops Master Slave Flip Flops Register: storing more than one bit, N bits Basic Building Blocks Decoders and Encoders Finite State Machines (FSM) How do we design logic circuits with state? Types of FSMs: Mealy and Moore Machines Examples: Serial Adder and a Digital Door Lock

9 Goal How do we store store one bit?

10 First Attempt: Unstable Devices B C A

11 First Attempt: Unstable Devices 10 B 01 A Does not work! Unstable Oscillates wildly! 01 C

12 Second Attempt: Bistable Devices Stable and unstable equilibria? A B A Simple Device A In stable state, A = B B A How do we change the state? B

13 Third Attempt: Set Reset Latch AS Q Q BR

14 Third Attempt: Set Reset Latch S Q R S R Q Q Set Reset (S R) Latch Stores a value Q and its complement

15 Third Attempt: Set Reset Latch 0 Q will be 0 if R is 1 S R Q Q ? 1? S 0 Q 1 1 R will be 1 Set Reset (S R) Latch Stores a value Q and its complement A B OR NOR

16 Third Attempt: Set Reset Latch 1 Q will be 1 S R Q Q ? 0? 1 1 S 1 Q 0 0 R will be 0 if S is 1 Set Reset (S R) Latch Stores a value Q and its complement A B OR NOR What are the values for Q and? a) 0 and 0 b) 0 and 1 c) 1 and 0 d) 1 and 1

17 Third Attempt: Set Reset Latch S R Q Q 0 0 Q? Q? If Q is 1, will stay 1 if Q is 0, will stay 0 S 1 0 Q 0 0 R If is 0will stay 0 If is 1 will stay 1 Set Reset (S R) Latch Stores a value Q and its complement A B OR NOR

18 Third Attempt: Set Reset Latch S R Q Q 0 0 Q Q ?? 0 S Q will be 0since R is 1 Q R will be 0 since S is 1 Set Reset (S R) Latch Stores a value Q and its complement A B OR NOR What happens when S,R changes from 1,1 to 0,0?

19 Third Attempt: Set Reset Latch S R Q Q 0 0 Q Q forbidden?? S Q R 1 0 Set Reset (S R) Latch Stores a value Q and its complement A B OR NOR What happens when S,R changes from 1,1 to 0,0? Q and Q become unstable and will oscillate wildly between values 0,0 to 1,1 to 0,0 to 1,1

20 Third Attempt: Set Reset Latch S S R Q Q S R Q Q 0 0 Q Q hold reset set R Set Reset (S R) Latch Stores a value Q and its complement 1 1 forbidden

21 Takeaway Set Reset (SR) Latch can store one bit and we can change the value of the stored bit. But, SR Latch has a forbidden state.

22 Next Goal How do we avoid the forbidden state of S R Latch?

23 Fourth Attempt: (Unclocked) D Latch D S D S R Q Q Q R D Q Fill in the truth table? 0 1 A B OR NOR

24 Fourth Attempt: (Unclocked) D Latch D S D S R Q Q Q Fill in the truth table? Data (D) Latch Easier to use than an SR latch No possibility of entering an undefined state When D changes, Q changes immediately ( after a delay of 2 Ors and 2 NOTs) Need to control when the output changes R D Q A B OR NOR

25 Takeaway Set Reset (SR) Latch can store one bit and we can change the value of the stored bit. But, SR Latch has a forbidden state. (Unclocked) D Latch can store and change a bit like an SR Latch while avoiding the forbidden state.

26 Next Goal How do we coordinate state changes to a D Latch?

27 Clocks Clock helps coordinate state changes Usually generated by an oscillating crystal Fixed period; frequency = 1/period 1 0 clock high clock period falling edge clock low rising edge

28 Clock Disciplines Level sensitive State changes when clock is high (or low) Edge triggered State changes at clock edge positive edge triggered negative edge triggered

29 Clock Methodology Clock Methodology Negative edge, synchronous clk t combinational t setup t hold compute save compute save compute Edge Triggered: Signals must be stable near falling clock edge Positive edge synchronous

30 Fifth Attempt: D Latch with Clock D S R Q

31 Fifth Attempt: D Latch with Clock D S Q clk R Fill in the truth table clk D Q

32 Fifth Attempt: D Latch with Clock D S Q clk R Fill in the truth table S R Q 0 0 Q hold reset set 1 1 forbidden clk D Q 0 0 Q 0 1 Q

33 D clk clk D Q Fifth Attempt: D Latch with Clock S R Q Level Sensitive D Latch Clock high: set/reset (according to D) Clock low: keep state (ignore D) clk D Q 0 0 Q 0 1 Q

34 Sixth Attempt: Edge Triggered D Flip Flop clk D X Q 1 D clk 0 0 D Q X D Q 1 L cl c 0 Q D Flip Flop Edge Triggered Data captured when clock is high Output changes only on falling edges Activity#1: Fill in timing graph and values for X and Q

35 Sixth Attempt: Edge Triggered D Flip Flop clk D X Q 01 D clk D Q X D Q 01 L cl c 10 Q D Flip Flop Edge Triggered Data captured when clock is high Output changes only on falling edges

36 Takeaway Set Reset (SR) Latch can store one bit and we can change the value of the stored bit. But, SR Latch has a forbidden state. (Unclocked) D Latch can store and change a bit like an SR Latch while avoiding a forbidden state. An Edge Triggered D Flip Flip (aka Master Slave D Flip Flip) stores one bit. The bit can be changed in a synchronized fashion on the edge of a clock signal.

37 Next Goal How do we store more than one bit, N bits?

38 Registers D0 D1 D2 Register D flip flops in parallel shared clock extra clocked inputs: write_enable, reset, D3 clk 4 bit 4 reg 4 clk

39 Takeaway Set Reset (SR) Latch can store one bit and we can change the value of the stored bit. But, SR Latch has a forbidden state. (Unclocked) D Latch can store and change a bit like an SR Latch while avoiding a forbidden state. An Edge Triggered D Flip Flip (aka Master Slave D Flip Flip) stores one bit. The bit can be changed in a synchronized fashion on the edge of a clock signal. An N bit register stores N bits. It is be created with N D Flip Flops in parallel along with a shared clock.

40 An Example: What will this circuit do? 4 Decoder bit reg +1 Clk 4

41 An Example: What will this circuit do? Reset Run WE R 4 Decoder bit reg Clk A[4] 1 = 0001 =B[4] C out +1 S[4] 4

42 Decoder Example: 7 Segment LED 7 Segment LED photons emitted when electrons fall into holes d7 d6 d5 d4 d3 d2 d1 d0

43 Decoder Example: 7 Segment LED 7 Segment LED photons emitted when electrons fall into holes d7 d6 d5 d4 d3 d2 d1 d0

44 Decoder Example: 7 Segment LED Decoder 7LED decode 3 inputs encode 0 7 in binary 7 outputs one for each LED

7 Segment LED Decoder Implementation b2 b1 b0 d6 d5 d4 d3 d2 d1 d0 0 0 0 0

45 7 Segment LED Decoder Implementation b2 b1 b0 d6 d5 d4 d3 d2 d1 d d1 d2 d0 d3 d4 d6 d5

46 7 Segment LED Decoder Implementation b2 b1 b0 d6 d5 d4 d3 d2 d1 d d1 d2 d0 d3 d4 d6 d5

47 Basic Building Blocks We have Seen 2 N binary encoder N N binary decoder 2 N N N N... N Multiplexor 2 M 1 N M

48 Encoders N Input wires N encoder... Log 2 (N) outputs wires e.g. Voting: Can only vote for one out of N candidates, so N inputs. But can encode vote efficiently with binary encoding.

49 Example Encoder Truth Table a 1 a b c d b 2 o o c 3 o 2 d 4 A 3-bit encoder with 4 inputs for simplicity

50 Example Encoder Truth Table a 1 a b c d o2 o1 o b 2 o o c 3 o 2 d 4 o2 = abcd A 3-bit encoder with 4 inputs for simplicity o1 = abcd + abcd o0 = abcd + abcd

51 Basic Building Blocks Example: Voting detect enc 7LED decode Ballots The 3410 optical scan vote reader machine

52 Recap We can now build interesting devices with sensors Using combinatorial logic We can also store data values (aka Sequential Logic) In state holding elements Coupled with clocks

53 Administrivia Make sure to go to your Lab Section this week Design Doc for Lab1 due Monday, Feb 4th Completed Lab1 due in two weeks, Monday, Feb 11th Work alone Homework1 is out Due in one week, next Wednesday, start early Homework Help Session: Thursday and Monday, B14 HLN, 6 8pm Work alone BUT, use your resources Lab Section, Piazza.com, Office Hours, Homework Help Session, Class notes, book, Sections, CSUGLab

54 Administrivia Check online syllabus/schedule Slides and Reading for lectures Office Hours Homework and Programming Assignments Prelims (in evenings): Tuesday, February 26 th Thursday, March 28 th Thursday, April 25 th Schedule is subject to change

55 Collaboration, Late, Re grading Policies Black Board Collaboration Policy Can discuss approach together on a black board Leave and write up solution independently Do not copy solutions Late Policy Each person has a total of four slip days Max of two slip days for any individual assignment Slip days deducted first for any late assignment, cannot selectively apply slip days For projects, slip days are deducted from all partners 25% deducted per day late after slip days are exhausted Regrade policy Submit written request to lead TA, and lead TA will pick a different grader Submit another written request, lead TA will regrade directly Submit yet another written request for professor to regrade.

56 Goals for Today State How do we store one bit? Attempts at storing (and changing) one bit Set Reset Latch D Latch D Flip Flops Master Slave Flip Flops Register: storing more than one bit, N bits Basic Building Blocks Decoders and Encoders Finite State Machines (FSM) How do we design logic circuits with state? Types of FSMs: Mealy and Moore Machines Examples: Serial Adder and a Digital Door Lock

57 Finite State Machines

58 Next Goal How do we design logic circuits with state?

59 Finite State Machines An electronic machine which has external inputs externally visible outputs internal state Output and next state depend on inputs current state

60 Abstract Model of FSM Machine is M = ( S, I, O, ) S: Finite set of states I: Finite set of inputs O: Finite set of outputs : State transition function Next state depends on present input and present state

61 Automata Model Finite State Machine Registers Current State Input Comb. Logic Output Next State inputs from external world outputs to external world internal state combinational logic

62 FSM Example input/output state Legend start state up/off up/off Input: up or down Output: on or off States: A, B, C, or D A C down/on up/off up/off B down/off D down/on up/off

63 FSM Example input/output state Legend start state up/off up/off A Input: = up or = down Output: = on or = off States: = A, = B, = C, or = D C down/on up/off up/off B down/off D down/on up/off

64 i 0 i 1 i 2 /o 0 o 1 o 2 S 1 S 0 FSM Example 1/1 0/0 1/1 S 1 S Legend 0/0 0/0 Input: 0=up or 1=down Output: 1=on or 1=off States: 00=A, 01=B, 10=C, or 11=D /0 0/0 1/0

65 Mealy Machine General Case: Mealy Machine Registers Current State Input Comb. Logic Output Next State Outputs and next state depend on both current state and input

66 Moore Machine Special Case: Moore Machine Registers Current State Input Comb. Logic Comb. Logic Output Next State Outputs depend only on current state

67 Moore Machine FSM Example input state out start out up A off down B on down Legend Input: up or down Output: on or off States: A, B, C, or D up C off up up down D off up

68 Mealy Machine FSM Example input/output state Legend start state up/off up/off Input: up or down Output: on or off States: A, B, C, or D A C down/on up/off up/off B down/off D down/on up/off

69 Activity#2: Create a Logic Circuit for a Serial Adder Add two infinite input bit streams streams are sent with least significant bit (lsb) first How many states are needed to represent FSM? Draw and Fill in FSM diagram Strategy: (1) Draw a state diagram (e.g. Mealy Machine) (2) Write output and next state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

70 FSM: State Diagram a b z Two states: S0 (no carry in), S1 (carry in) Inputs: aand b Output: z z is the sum of inputs a, b, and carry in (one bit at a time) A carry out is the next carry in state..

71 FSM: State Diagram / /_ S0 /_ S1 / / / / /_ a b z Two states: S0 (no carry in), S1 (carry in) Inputs: aand b Output: z z is the sum of inputs a, b, and carry in (one bit at a time) A carry out is the next carry in state. Arcs labeled with input bits a and b, and output z

72 FSM: State Diagram 11/0 00/0 S0 00/1 S1 11/1 10/1 01/1 10/0 01/0 a b z Two states: S0 (no carry in), S1 (carry in) Inputs: aand b Output: z z is the sum of inputs a, b, and carry in (one bit at a time) A carry out is the next carry in state. Arcs labeled with input bits a and b, and output z (Mealy Machine)

73 Serial Adder: State Table 11/0 00/0 S0 00/1 S1 11/1 10/1 01/1 10/0 01/0 a b Current state z Next state (2) Write down all input and state combinations

74 Serial Adder: State Table 11/0 00/0 S0 00/1 S1 11/1 10/1 01/1 10/0 01/0 a b Current state z Next state 0 0 S0 0 S0 0 1 S0 1 S0 1 0 S0 1 S0 1 1 S0 0 S1 0 0 S1 1 S0 0 1 S1 0 S1 1 0 S1 0 S1 1 1 S1 1 S1 (2) Write down all input and state combinations

75 Serial Adder: State Assignment 11/0 00/0 0 00/1 1 11/1 10/1 01/1 10/0 01/0 a b s z s' (3) Encode states, inputs, and outputs as bits Two states, so 1 bit is sufficient A single flip flop will encode the state

76 Next State s' Serial Adder: Circuit Current Output State D Q s Comb. z a Logic b Next State Input s' a b s z s' (4) Determine logic equations for next state and outputs Combinational Logic Equations z= b + a + s + abs s = ab + bs + a s + abs

77 Next State s' Sequential Logic Circuits Current Output State D Q s Comb. z a Logic b Next State Input s' z= b + a + s + abs s = ab + bs + a s + abs Strategy:. (1) Draw a state diagram (e.g.. Mealy Machine) (2) Write output and next state. tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

78 Example #2: Digital Door Lock Digital Door Lock Inputs: keycodes from keypad clock Outputs: unlock signal display how many keys pressed so far

79 Door Lock: Inputs Assumptions: signals are synchronized to clock Password is B A B K A B K A B Meaning Ø (no key) A pressed B pressed

80 D 3 D 2 D 1 D 0 4 LED dec 8 U Door Lock: Outputs Assumptions: High pulse on U unlocks door Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

81 Door Lock: Simplified State Diagram B Ø Ø G1 A G2 B G , U else else any Ø Idle 0 else B1 else B2 1 2 Ø Ø else any B3 3 (1) Draw a state diagram (e.g. Moore Machine)

82 Door Lock: Simplified State Diagram B Ø Ø G1 A G2 B G , U else else any Idle 0 Ø else else B1 else B2 1 2 Ø Ø (1) Draw a state diagram (e.g. Moore Machine)

83 Ø Door Lock: Simplified State Diagram Idle 0 B else Ø Ø G1 A G2 B G , U else B1 else B2 1 2 Ø else else (2) Write output and next state tables Ø Cur. State any Output

84 Ø Door Lock: Simplified State Diagram Idle 0 B else Ø Ø G1 A G2 B G , U else else B1 else B2 1 2 else Ø Ø (2) Write output and next state tables Cur. any Output State Idle 0 G1 1 G2 2 G3 3, U B1 1 B2 2

85 Door Lock: Simplified State Diagram B Ø Ø G1 A G2 B G , U else Cur. State Input Next State else any Idle 0 Ø else else B1 else B2 1 2 Ø Ø (2) Write output and next state tables

86 Ø Door Lock: Simplified State Diagram Idle 0 B else Ø Ø G1 A G2 B G , U else else B1 else B2 1 2 Cur. State Input Next State else Idle Ø Idle Idle B G1 Idle A B1 G1 Ø G1 any G1 A G2 G1 B B2 G2 Ø B2 G2 B G3 G2 A Idle G3 any Idle B1 Ø B1 B1 K B2 B2 Ø B2 Ø Ø B2 K Idle (2) Write output and next state tables

State K A B Meaning S 2 S 1 S 0 0 Idle 0 0 Ø 0 (no 0 key) 0 U 1 G1 1 0 A 0 pressed 0 1 1 G2 0 1 B 0 pressed 1 0 G3 0 1 1 D 3 D 2 D 1 D 0 4 dec 8 State Table Encoding SCur.

87 State K A B Meaning S 2 S 1 S 0 0 Idle 0 0 Ø 0 (no 0 key) 0 U 1 G1 1 0 A 0 pressed G2 0 1 B 0 pressed 1 0 G D 3 D 2 D 1 D 0 4 dec 8 State Table Encoding SCur. 2 SState 1 S 0 D 3 DOutput 2 D 1 D 0 U Cur. S 2 SState 1 S 0 K Input A B S Next 2 S State 1 S 0 0 Idle Idle Ø0 0 0 Idle G Idle B G G Idle A B G , 1 U1 1 0 G Ø0 0 0 G B G A G B G B B2 0 1 K A B B (3) Encode states, inputs, and outputs as bits B G Ø0 0 0 B G B G G A Idle G3 1 1 x any x x 0 Idle B Ø0 0 1 B B Kx x 1 B B Ø0 0 1 B B Kx x 0 Idle 0 0

88 Door Lock: Implementation 3bit Reg S 2 0 D 3 0 U 4 dec clk S 2 0 U = 2S 1 S 0 D 0 = 2 1S 0 + 2S 1 S 0 + S D 1 = 2S 1 S 0 + 2S 1 S 0 + 2S 1 S 0 S 2 S 1 S 0 D 3 D 2 D 1 D 0 U KA B S (4) Determine logic equations for next state and outputs

89 Door Lock: Implementation 3bit Reg clk S 2 0 S 2 0 K A B S 2 S 1 S 4 0 K A B S 2 S 1 S 0 D U S x x x x x x x S 2 = S 2 S 1 S 0 KAB + S 2 S 1 S 0 KA B + S 2 S 1 S 2 KAB + S 2 S 1 S 0 K + S 2 S 1 S 0 KAB dec

90 Door Lock: Implementation 3bit Reg S 2 0 D 3 0 U 4 dec clk S 2 0 K A B S 2 0 Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs

91 Summary We can now build interesting devices with sensors Using combinational logic We can also store data values Stateful circuit elements (D Flip Flops, Registers, ) Clock to synchronize state changes State Machines or Ad Hoc Circuits

State & Finite State Machines

State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Big Picture: Building a Processor memory inst register file