Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts

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1 ed Sequential Circuits 2 Contents nalysis by signal tracing & timing charts State tables and graphs General models for sequential circuits sequential parity checker Reading Unit 3 asic unit Unit : Latch & FFs UNIT 3 NLYSIS OF CLOED SEUENTIL CIRCUITS asically, no inputs Simple sequential Ckt Unit 2: Registers & Counters Complex sequential Ckt Units 3-5: FSM Iris Hui-Ru Jiang Spring 2 ed sequential ckt Put it all together Unit 6: Summary nalysis of ed Sequential Circuits 3 Find the output sequence resulting from a given input one Draw a timing chart to show inputs, clock, FF s, outputs. ssume an initial of FFs (reset to ) 2. Determine the circuit outputs & FF inputs for st input pattern 3. Determine the new FF s after the next active clock edge 4. Determine the outputs for the new s 5. Repeat 2 4 for each input pattern 4 Signal Tracing and Timing Charts Current s s Current inputs trigger Current outputs ed sequential ckt ed sequential ckt

2 5 Type I: Moore Machine Moore machine: the output depends only on the present The output which corresponds to a given input appears until after the active clock edge D ed sequential ckt D = () () () () 6 Type II: Mealy Machine Mealy machine: the output depends on both the present and on the inputs False outputs may occur Glitches and spikes () () False output ed sequential ckt False output K J K J How to Construct the State Table? 8 The table specifies 7 State Tables and Graphs Output Input Procedure to construct the table for a given circuit. Determine the flip-flop input equations and the output equations from the circuit 2. Derive the next- equation for each FF from its input equations 3. Plot a next- map for each flip-flop 4. Combine these maps to form the table ed sequential ckt ed sequential ckt

3 9 Recap Next-State Equations Type D FF = D Example: Moore Machine (/2). D = D = = 2. = = 3. D-CE FF = DCE CE' T FF = T S-R FF = S R' (SR = ) J-K FF = J K D D 4. = = ed sequential ckt Example: Moore Machine (2/2) = = State assignment S S 2 Example: Mealy Machine (/3).&2. = J K = = J K = () = = 3. K J K J S S = = S S ed sequential ckt S S output () () () () ()

4 Example: Mealy Machine (2/3) Example: Mealy Machine (3/3) 3 / 4 / / S / / / / S / / / / S / / S / / / State graph = = 4. ed sequential ckt = = State assignment S S = = S S S S S output () = = ed sequential ckt () () False output False output 5 x i y i Example: Serial dder s i c i c i D x i y i c i c i s i /// /// x i y i /s i S / S / S : c i =; S : c i = Carry_out (c i ) is latched in the DFF The latched Carry_out will be added with the next x i and y i x i y i c i c i s i glitch 6 S S Example: Multiple Inputs and Outputs 2 = S S S ed sequential ckt S S S S S S : Input = Output =? (check by yourself) State transition : S S output ( 2 ) 2 =, / / S / / / / / / / / / / S / //

5 General Model for Mealy Machines 7 General Models Moore vs. Mealy 8 n output is a function of s and inputs 2 m Combinational Subcircuit 2 n D D 2 D k ed sequential ckt ed sequential ckt General Model for Moore Machines 9 n output is a function of only s 2 m Combinational Subcircuit (For Flip-Flop Inputs) D D 2 Combinational Subcircuit (For Outputs) 2 n 2 Case Study: Sequential Parity Checker D k ed sequential ckt ed sequential ckt

6 Parity Checker (/3) Parity Checker (2/3) 2 Error detection: add an extra bit (parity bit) when transmitting or storing binary data When the total # of bits in the block (data bits parity bit) is odd (even), we say the parity is odd (even) Even parity Odd parity 22 Design an odd-parity checker = if total # of s is odd Parity = if total # of s is even (Data Input) Checker = an error occurs in odd-parity protocol Initially, = Timing chart of the odd parity checker (active-low) Data bits Parity bits = ed sequential ckt ed sequential ckt Parity Checker (3/3) Homework for Unit 3 23 = S S State graph S = Even State table = = = = S S S S S = Odd output () = Implementation T = = 24 Problems Hint: data should be ready before the clock edge Homework #5: Units 2 3 Due am May 25, 2 uiz #5: due day of Homework #5 ed sequential ckt ed sequential ckt